Design of a 150 mV Supply, 2 MIPS, 90nm CMOS, Ultra-Low-Power Microprocessor

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7606)


This work presents a simulated ultra-low-power 16-bit sub-threshold microprocessor designed in a 90nm CMOS technology. Transmission gate logic extended with transistor stacking is used for its high robustness to inter- and intra-die variations, while combining low power and small area. In a first implementation, the sub-threshold microprocessor has a throughput of 1MIPS at a 4MHz clock and a 150mV supply with an energy per instruction of 0.74pJ. Improved results are obtained using pipelining, which allows the microprocessor to achieve a maximum performance of 2MIPS, an energy consumption of 0.48pJ per instruction, an EDP of 0.23pJ×μs and a 0.9μW power consumption.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.ESAT-MICASKatholieke Universiteit LeuvenLeuvenBelgium
  2. 2.imec vzw.LeuvenBelgium

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