Byte Slicing Grøstl: Improved Intel AES-NI and Vector-Permute Implementations of the SHA-3 Finalist Grøstl

  • Kazumaro Aoki
  • Krystian Matusiewicz
  • Günther Roland
  • Yu Sasaki
  • Martin Schläffer
Part of the Communications in Computer and Information Science book series (CCIS, volume 314)

Abstract

Grøstl is an AES-based hash function and one of the 5 finalists of the SHA-3 competition. In this work we present high-speed implementations of Grøstl for small 8-bit CPUs, and large 64-bit CPUs with the recently introduced Intel AES-NI and AVX instruction sets. Since Grøstl does not use the same MDS mixing layer as the AES, a direct application of the AES instructions seems difficult. In contrast to previous findings, our Grøstl implementations using the AES instructions are currently by far the fastest known. To achieve optimal performance we parallelize each round of Grøstl by taking advantage of the whole bit width of the used processor. This results in the parallel computation of 16 Grøstl columns using 128-bit registers, and 32 Grøstl columns using 256-bit registers. This way, we get implementations running at 12.2 cylces/byte for Grøstl-256 and 18.6 cylces/byte for Grøstl-512.

Keywords

Hash function SHA-3 competition Grøstl Software implementation Byte slicing Intel AES new instructions 8-bit AVR 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Kazumaro Aoki
    • 1
  • Krystian Matusiewicz
    • 2
  • Günther Roland
    • 3
  • Yu Sasaki
    • 1
  • Martin Schläffer
    • 3
  1. 1.NTT CorporationJapan
  2. 2.Intel TechnologyPoland
  3. 3.IAIK, Graz University of TechnologyAustria

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