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Real-Time Runtime Verification on Chip

  • Thomas Reinbacher
  • Matthias Függer
  • Jörg Brauer
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7687)

Abstract

We present an algorithmic framework that allows on-line monitoring of past-time MTL specifications in a discrete time setting. The algorithms allow to be synthesized into efficient observer hardware blocks, which take advantage of the highly-parallel nature of hardware designs. For the time-bounded Since operator of past-time MTL we obtain a time complexity that is double logarithmic in the time it is executed at and the given time bounds of the Since operator. This result is promising with respect to a non-interfering monitoring approach that evaluates real-time specifications during the execution of the system-under-test. The resulting hardware blocks are reconfigurable and have applications in prototyping and runtime verification of embedded real-time systems.

Keywords

Temporal Logic Space Complexity Garbage Collection Parse Tree Atomic Proposition 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  • Thomas Reinbacher
    • 1
  • Matthias Függer
    • 1
  • Jörg Brauer
    • 2
    • 3
  1. 1.Embedded Computing Systems GroupVienna University of TechnologyAustria
  2. 2.Verified Systems International GmbHBremenGermany
  3. 3.Embedded Software LaboratoryRWTH Aachen UniversityGermany

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