Multi-precision Multiplication for Public-Key Cryptography on Embedded Microprocessors
In this paper, we revisit the “operand caching” method for multi-precision multiplication, which reduces the number of required load instructions by caching the operands . With the previous method, we can achieve high performance in terms of multiplication speed with modern micro-processors. However, this method does not provide full operand caching when changing the row of partial products. To overcome this problem, we propose a novel method, i.e., “consecutive operand caching”. We divide partial products and reconstruct them yielding common operands between previous and new partial products. Finally, we reduce the number of load instructions and boost the speed of multi-precision multiplication by 3.85%, as compared to previous best known results.
KeywordsMulti-precision Multiplication Public-Key Cryptography Consecutive Operand-Caching Method Embedded Microprocessors
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