Compact Hardware Implementations of the Block Ciphers mCrypton, NOEKEON, and SEA

  • Thomas Plos
  • Christoph Dobraunig
  • Markus Hofinger
  • Alexander Oprisnik
  • Christoph Wiesmeier
  • Johannes Wiesmeier
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7668)


Compact hardware implementations are important for enabling security services on constrained devices like radio-frequency identification (RFID) tags or sensor nodes where chip area is highly limited. In this work we present compact hardware implementations of the block ciphers: mCrypton, NOEKEON, and SEA. Our implementations are significantly smaller in terms of chip area than the results available in related work. In case of NOEKEON, we even provide the first hardware-implementation results of this algorithm at all. Our implementations are designed as stand-alone hardware modules, contain an 8-bit interface for communication, and support encryption as well as decryption operation. We give results for different datapath widths and evaluate also the impact of using shift registers or latch-based memory instead of flip flops. The most-compact implementation of mCrypton requires 2 709 GEs when using a 130 nm CMOS process technology from Faraday. NOEKEON and SEA consume 2 880 and 2 562 GEs, respectively.


low-resource hardware implementation RFID symmetric cryptography block cipher low power consumption shift register 8-bit interface 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    AMS. Standard Cell Library 0.35μm CMOS (C35),
  2. 2.
    ARM Ltd. AMBA Advanced Microcontroller Bus Architecture Specification, (1997)
  3. 3.
    Atmel Corporation. 8-bit AVR Microcontroller with 128K Bytes In-System Programmable Flash (August 2007),
  4. 4.
    Daemen, J., Peeters, M., Assche, G.V., Rijmen, V.: Nessie proposal: NOEKEON (2000),
  5. 5.
    Faraday Technology Corporation. Faraday FSA0A_C 0.13 μm ASIC Standard Cell Library (2004),
  6. 6.
    Faraday Technology Corporation. Faraday FSA0A_C 0.18 μm ASIC Standard Cell Library (2004),
  7. 7.
    Feldhofer, M., Wolkerstorfer, J.: Hardware Implementation of Symmetric Algorithms for RFID Security. In: RFID Security: Techniques, Protocols and System-On-Chip Design, pp. 373–415. Springer (2008)Google Scholar
  8. 8.
    Feldhofer, M., Wolkerstorfer, J., Rijmen, V.: AES Implementation on a Grain of Sand. IEEE Proceedings on Information Security 152(1), 13–20 (2005)CrossRefGoogle Scholar
  9. 9.
    Hämäläinen, P., Alho, T., Hännikäinen, M., Hämäläinen, T.D.: Design and Implementation of Low-Area and Low-Power AES Encryption Hardware Core. In: Conference on Digital System Design (DSD 2006), pp. 577–583. IEEE (September 2006)Google Scholar
  10. 10.
    Hong, D., Sung, J., Hong, S., Lim, J., Lee, S., Koo, B.-S., Lee, C., Chang, D., Lee, J., Jeong, K., Kim, H., Kim, J., Chee, S.: HIGHT: A New Block Cipher Suitable for Low-Resource Device. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 46–59. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  11. 11.
    Knudsen, L.R., Raddum, H.: On Noekeon NES/DOC/UIB/WP3/009/1 (2001),
  12. 12.
    Kumar, K.J., Salivahanan, S., Reddy, K.C.K.: Implementation of Low Power Scalable Encryption Algorithm. International Journal of Computer Applications 11(1), 14–18 (2010)CrossRefGoogle Scholar
  13. 13.
    Lim, C.H., Korkishko, T.: mCrypton – A Lightweight Block Cipher for Security of Low-Cost RFID Tags and Sensors. In: Song, J.-S., Kwon, T., Yung, M. (eds.) WISA 2005. LNCS, vol. 3786, pp. 243–258. Springer, Heidelberg (2006), doi:10.1007/11604938CrossRefGoogle Scholar
  14. 14.
    Mace, F., Standaert, F.-X., Quisquater, J.-J.: ASIC Implementations of the Block Cipher SEA for Constrained Applications. In: Workshop on RFID Security (RFIDSec 2007), pp. 103–114 (2007)Google Scholar
  15. 15.
    Mala, H., Dakhilalian, M., Shakiba, M.: Cryptanalysis of mCrypton - A lightweight block cipher for security of RFID tags and sensors. International Journal of Communication Systems 25(4), 415–426 (2012)CrossRefGoogle Scholar
  16. 16.
    Moradi, A., Poschmann, A., Ling, S., Paar, C., Wang, H.: Pushing the Limits: A Very Compact and a Threshold Implementation of AES. In: Paterson, K.G. (ed.) EUROCRYPT 2011. LNCS, vol. 6632, pp. 69–88. Springer, Heidelberg (2011)CrossRefGoogle Scholar
  17. 17.
    Standaert, F.-X., Piret, G., Gershenfeld, N., Quisquater, J.-J.: SEA: A Scalable Encryption Algorithm for Small Embedded Applications. In: Domingo-Ferrer, J., Posegga, J., Schreckling, D. (eds.) CARDIS 2006. LNCS, vol. 3928, pp. 222–236. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  18. 18.
    Texas Instruments. MSP430C11x1 - Mixed Signal Microcontroller (2008),
  19. 19.
    Z’aba, M.R., Raddum, H., Henricksen, M., Dawson, E.: Bit-Pattern Based Integral Attack. In: Nyberg, K. (ed.) FSE 2008. LNCS, vol. 5086, pp. 363–381. Springer, Heidelberg (2008)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Thomas Plos
    • 1
  • Christoph Dobraunig
    • 1
  • Markus Hofinger
    • 1
  • Alexander Oprisnik
    • 1
  • Christoph Wiesmeier
    • 1
  • Johannes Wiesmeier
    • 1
  1. 1.Institute for Applied Information Processing and Communications (IAIK)Graz University of TechnologyGrazAustria

Personalised recommendations