Cyfield-RISP: Generating Dynamic Instruction Set Processors for Reconfigurable Hardware Using OpenCL

  • Jörn Hoffmann
  • Frank Güttler
  • Karim El-Laithy
  • Martin Bogdan
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7552)

Abstract

In this work a novel approach to automatically generate hardware is introduced that allows accelerated simulation of artificial neural networks (ANN) on field-programming gate arrays (FPGAs). A compiler architecture has been designed that primarily aims at reducing the development effort for non-hardware developers. This is done by implementing automatic generation of accordingly adjusted hardware processors. Deduced from high-level OpenCL source code, the processors are able to spatially map ANNs in a massive parallel fashion.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Jörn Hoffmann
    • 1
  • Frank Güttler
    • 1
  • Karim El-Laithy
    • 1
  • Martin Bogdan
    • 1
  1. 1.Faculty of Mathematics and Computer Science, Dept. of Computer EngineeringUniversität LeipzigGermany

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