Pushing the Limits of High-Speed GF(2m) Elliptic Curve Scalar Multiplication on FPGAs

  • Chester Rebeiro
  • Sujoy Sinha Roy
  • Debdeep Mukhopadhyay
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7428)


In this paper we present an FPGA implementation of a high-speed elliptic curve scalar multiplier for binary finite fields. High speeds are achieved by boosting the operating clock frequency while at the same time reducing the number of clock cycles required to do a scalar multiplication. To increase clock frequency, the design uses optimized implementations of the underlying field primitives and a mathematically analyzed pipeline design. To reduce clock cycles, a new scheduling scheme is presented that allows overlapped processing of scalar bits. The resulting scalar multiplier is the fastest reported implementation for generic curves over binary finite fields. Additionally, the optimized primitives leads to area requirements that is significantly lesser compared to other high-speed implementations. Detailed implementation results are furnished in order to support the claims.


Elliptic curve scalar multiplication FPGA high-speed implementation Montgomery ladder 


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Copyright information

© International Association for Cryptologic Research 2012

Authors and Affiliations

  • Chester Rebeiro
    • 1
  • Sujoy Sinha Roy
    • 1
  • Debdeep Mukhopadhyay
    • 1
  1. 1.Department of Computer Science and EngineeringIndian Institute of Technology KharagpurIndia

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