Improved BDD-Based Discrete Analysis of Timed Systems

  • Truong Khanh Nguyen
  • Jun Sun
  • Yang Liu
  • Jin Song Dong
  • Yan Liu
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7436)

Abstract

Model checking timed systems through digitization is relatively easy, compared to zone-based approaches. The applicability of digitization, however, is limited mainly for two reasons, i.e., it is only sound for closed timed systems; and clock ticks cause state space explosion. The former is mild as many practical systems are subject to digitization. It has been shown that BDD-based techniques can be used to tackle the latter to some extent. In this work, we significantly improve the existing approaches by keeping the ticks simple in the BDD encoding. Taking advantage of the ‘simple’ nature of clock ticks, we fine-tune the encoding of ticks and are able to verify systems with many ticks. Furthermore, we develop a BDD library which supports not only encoding/verifying of timed state machines (through digitization) but also composing timed components using a rich set of composition functions. The usefulness and scalability of the library are demonstrated by supporting two languages, i.e., closed timed automata and Stateful Timed CSP.

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References

  1. 1.
    Berthomieu, B., Menasche, M.: An Enumerative Approach for Analyzing Time Petri Nets. In: IFIP Congress, pp. 41–46 (1983)Google Scholar
  2. 2.
    Dill, D.L.: Timing Assumptions and Verification of Finite-State Concurrent Systems. In: Sifakis, J. (ed.) CAV 1989. LNCS, vol. 407, pp. 197–212. Springer, Heidelberg (1990)CrossRefGoogle Scholar
  3. 3.
    Havelund, K., Skou, A., Larsen, K.G., Lund, K.: Formal Modeling and Analysis of an Audio/video Protocol: an Industrial Case Study using UPPAAL. In: RTSS, pp. 2–13 (1997)Google Scholar
  4. 4.
    Henzinger, T.A., Manna, Z., Pnueli, A.: What Good Are Digital Clocks? In: Kuich, W. (ed.) ICALP 1992. LNCS, vol. 623, pp. 545–558. Springer, Heidelberg (1992)CrossRefGoogle Scholar
  5. 5.
    Lamport, L.: Real-Time Model Checking Is Really Simple. In: Borrione, D., Paul, W. (eds.) CHARME 2005. LNCS, vol. 3725, pp. 162–175. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  6. 6.
    Tripakis, S.: Verifying Progress in Timed Systems. In: Katoen, J.-P. (ed.) AMAST-ARTS 1999, ARTS 1999, and AMAST-WS 1999. LNCS, vol. 1601, pp. 299–314. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  7. 7.
    Herbreteau, F., Srivathsan, B., Walukiewicz, I.: Efficient Emptiness Check for Timed Büchi Automata. In: Touili, T., Cook, B., Jackson, P. (eds.) CAV 2010. LNCS, vol. 6174, pp. 148–161. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  8. 8.
    Beyer, D., Lewerentz, C., Noack, A.: Rabbit: A Tool for BDD-Based Verification of Real-Time Systems. In: Hunt Jr., W.A., Somenzi, F. (eds.) CAV 2003. LNCS, vol. 2725, pp. 122–125. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  9. 9.
    Beyer, D., Noack, A.: Can Decision Diagrams Overcome State Space Explosion in Real-Time Verification? In: König, H., Heiner, M., Wolisz, A. (eds.) FORTE 2003. LNCS, vol. 2767, pp. 193–208. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  10. 10.
    Sun, J., Liu, Y., Dong, J.S., Liu, Y., Shi, L., André, E.: Modeling and Verifying Hierarchical Real-time Systems using Stateful Timed CSP. ACM Transactions on Software Engineering and Methodology (2011) (to appear)Google Scholar
  11. 11.
    Nguyen, T.K., Sun, J., Liu, Y., Dong, J.S., Liu, Y.: BDD-based Discrete Analysis of Timed Systems, http://www.comp.nus.edu.sg/%7Epat/bddlib/
  12. 12.
    Burch, J.R., Clarke, E.M., Long, D.E.: Symbolic Model Checking with Partitioned Transistion Relations. In: VLSI, pp. 49–58 (1991)Google Scholar
  13. 13.
    Alur, R., Dill, D.L.: A Theory of Timed Automata. Theoretical Computer Science 126, 183–235 (1994)MathSciNetMATHCrossRefGoogle Scholar
  14. 14.
    Jin, X.L., Ma, H.D., Gu, Z.H.: Real-Time Component Composition Using Hierarchical Timed Automata. In: QSIC, pp. 90–99. IEEE (2007)Google Scholar
  15. 15.
    David, A., David, R., Möller, M.O.: From HUPPAAL to UPPAAL - A Translation from Hierarchical Timed Automata to Flat Timed Automata. Technical report, Department of Computer Science, University of Aarhus (2001)Google Scholar
  16. 16.
    Hoare, C.A.R.: Communicating Sequential Processes. International Series in Computer Science. Prentice-Hall (1985)Google Scholar
  17. 17.
    Sun, J., Liu, Y., Dong, J.S., Pang, J.: PAT: Towards Flexible Verification under Fairness. In: Bouajjani, A., Maler, O. (eds.) CAV 2009. LNCS, vol. 5643, pp. 709–714. Springer, Heidelberg (2009)CrossRefGoogle Scholar
  18. 18.
    Liu, Y., Sun, J., Dong, J.S.: Developing Model Checkers Using PAT. In: Bouajjani, A., Chin, W.-N. (eds.) ATVA 2010. LNCS, vol. 6252, pp. 371–377. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  19. 19.
    Vardi, M.Y., Wolper, P.: An Automata-Theoretic Approach to Automatic Program Verification. In: LICS, pp. 332–344. IEEE Computer Society (1986)Google Scholar
  20. 20.
    Wang, H., MacCaull, W.: Verifying Real-Time Systems using Explicit-time Description Methods. In: QFM. EPTCS, vol. 13, pp. 67–78 (2009)Google Scholar
  21. 21.
    Morbé, G., Pigorsch, F., Scholl, C.: Fully Symbolic Model Checking for Timed Automata. In: Gopalakrishnan, G., Qadeer, S. (eds.) CAV 2011. LNCS, vol. 6806, pp. 616–632. Springer, Heidelberg (2011)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Truong Khanh Nguyen
    • 2
  • Jun Sun
    • 1
  • Yang Liu
    • 2
  • Jin Song Dong
    • 2
  • Yan Liu
    • 2
  1. 1.Information System Technology and DesignSingapore University of Technology and DesignSingapore
  2. 2.School of ComputingNational University of SingaporeSingapore

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