Domain-Knowledge Optimized Simulated Annealing for Network-on-Chip Application Mapping

  • Ciprian RaduEmail author
  • Lucian Vinţan
Part of the Advances in Intelligent Systems and Computing book series (AISC, volume 187)


Network-on-Chip architectures are scalable on-chip interconnection networks. They replace the inefficient shared buses and are suitable for multicore and manycore systems. This paper presents an Optimized Simulated Annealing (OSA) algorithm for the Network-on-Chip application mapping problem. With OSA, the cores are implicitly and dynamically clustered using knowledge about communication demands. We show that OSA is a more feasible Simulated Annealing approach to NoC application mapping by comparing it with a general Simulated Annealing algorithm and a Branch and Bound algorithm, too. Using real applications we show that OSA is significantly faster than a general Simulated Annealing, without giving worse solutions. OSA proves to be feasible for Networks-on-Chip with more than 100 nodes. Also, compared to a Branch and Bound technique, it gives better solutions, as the problem size increases, while in terms of speed and memory consumption the two algorithms are comparable.


Network-on-Chip (NoC) application mapping clustering optimization evaluation simulation 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Kirkpatrick, S., Gelatt, C., Vecchi, M.: Optimization by Simulated Annealing. Science 220, 671–680 (1983)MathSciNetzbMATHCrossRefGoogle Scholar
  2. 2.
    Fouskakis, D., Draper, D.: Stochastic Optimization: a Review. International Statistical Review 70, 315–349 (2007)CrossRefGoogle Scholar
  3. 3.
    Hu, J., Marculescu, R.: Energy-aware mapping for tile-based NoC architectures under performance constraints. In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference, pp. 233–239. ACM, Kitakyushu (2003)CrossRefGoogle Scholar
  4. 4.
    Hu, J., Marculescu, R.: Energy- and performance-aware mapping for regular NoC architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 24, 551–562 (2005)CrossRefGoogle Scholar
  5. 5.
    Lu, Z., Xia, L., Jantsch, A.: Cluster-based Simulated Annealing for Mapping Cores onto 2D Mesh Networks on Chip. In: Proceedings of the 2008 11th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp. 1–6. IEEE Computer Society, Washington, DC (2008)CrossRefGoogle Scholar
  6. 6.
    SLD: System Level Design Group @ CMU: NoCmap: an energy- and performance-aware mapping tool for Networks-on-Chip,
  7. 7.
    Radu, C., Vinţan, L.: Unimap: Unified Framework For Network-On-Chip Application Mapping Research. Acta Universitatis Cibiniensis Technical Series (2011)Google Scholar
  8. 8.
    Radu, C., Vinţan, L.: Optimizing Application Mapping Algorithms for NoCs through a Unified Framework. In: 2010 9th Roedunet International Conference (RoEduNet), pp. 259–264. IEEE Computer Society, Sibiu (2010)Google Scholar
  9. 9.
    Orsila, H., Salminen, E., Hämäläinen, T.D.: Best Practices for Simulated Annealing in Multiprocessor Task Distribution Problems. Simulated Annealing, pp. 321–342. I-Tech Education and Publishing KG (2008)Google Scholar
  10. 10.
  11. 11.
    The Embedded System Synthesis Benchmarks Suite (E3S) website,
  12. 12.
    Marculescu, R., Ogras, U.Y., Peh, L.-S., Jerger, N.E., Hoskote, Y.: Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives. Trans. Comp.-Aided Des. Integ. Cir. Sys. 28, 3–21 (2009)CrossRefGoogle Scholar
  13. 13.
    Murali, S., Micheli, G.D.: Bandwidth-Constrained Mapping of Cores onto NoC Architectures. In: Proceedings of the Conference on Design, Automation and Test in Europe, vol. 2, pp. 896–903. IEEE Computer Society, Paris (2004)CrossRefGoogle Scholar
  14. 14.
    Murali, S., Micheli, G.D.: SUNMAP: a tool for automatic topology selection and generation for NoCs. In: Proceedings of the 41st Annual Design Automation Conference, pp. 914–919. ACM, San Diego (2004)CrossRefGoogle Scholar
  15. 15.
    Radu, C., Vinţan, L.: Optimized Simulated Annealing for Network-on-Chip Application Mapping. In: Proceedings of the 18th International Conference on Control Systems and Computer Science (CSCS-18), pp. 452–459. Politehnica Press, Bucharest (2011)Google Scholar
  16. 16.
    Radu, C.: Optimized Algorithms for Network-on-Chip Application Mapping. “Lucian Blaga” University of Sibiu, Romania (2011)Google Scholar
  17. 17.
    Lungu, V., Sofron, A.: Using Particle Swarm Optimization to Create Particle Systems. In: Proceedings of the 18th International Conference on Control Systems and Computer Science (CSCS-18), pp. 750–754. Politehnica Press, Bucharest (2011)Google Scholar
  18. 18.
    Calborean, H., Jahr, R., Ungerer, T., Vintan, L.: Optimizing a Superscalar System using Multi-objective Design Space Exploration. In: Proceedings of the 18th International Conference on Control Systems and Computer Science (CSCS), Bucharest, Romania, pp. 339–346 (2011)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2013

Authors and Affiliations

  1. 1.Advanced Computer Architecture & Processing Systems Research Lab“Lucian Blaga” University of SibiuSibiuRomania

Personalised recommendations