Efficient FPGA Implementation of Montgomery Multiplier Using DSP Blocks
In this paper, an efficient Montgomery modular multiplier is designed exploiting the efficiency of inbuilt multiplier and adder soft-cores of DSP blocks. 256×256 bit multiplier has been implemented with (i) fully parallel, (ii) pipelined and (iii) semi parallel architectures that consumes upto 16 DSP48E1 64×64 bit soft-cores provided by Xilinx 12.4 ISE Design Suite. Performances with respect to area, operating frequency and design latency have been compared.
KeywordsMontgomery Multiplier FPGA design DSP blocks
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