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Efficient FPGA Implementation of Montgomery Multiplier Using DSP Blocks

  • Arpan Mondal
  • Santosh Ghosh
  • Abhijit Das
  • Dipanwita Roy Chowdhury
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7373)

Abstract

In this paper, an efficient Montgomery modular multiplier is designed exploiting the efficiency of inbuilt multiplier and adder soft-cores of DSP blocks. 256×256 bit multiplier has been implemented with (i) fully parallel, (ii) pipelined and (iii) semi parallel architectures that consumes upto 16 DSP48E1 64×64 bit soft-cores provided by Xilinx 12.4 ISE Design Suite. Performances with respect to area, operating frequency and design latency have been compared.

Keywords

Montgomery Multiplier FPGA design DSP blocks 

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References

  1. 1.
    Huang, G., El-Ghazawi: New Hardware Architectures for Montgomery Modular Multiplication Algorithm. IEEE Transactions on Computers, 923–936 (2011)Google Scholar
  2. 2.
    Montgomery, P.: Modular multiplication without trial division. Mathematics of Computation 44(170), 519–521 (1985)MathSciNetzbMATHCrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Arpan Mondal
    • 1
  • Santosh Ghosh
    • 1
  • Abhijit Das
    • 1
  • Dipanwita Roy Chowdhury
    • 1
  1. 1.Department of Computer Science and EngineeringIIT KharagpurIndia

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