Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip

  • Bibhas Ghoshal
  • Subhadip Kundu
  • Indranil Sengupta
  • Santanu Chattopadhyay
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7373)

Abstract

Network-on-Chip (NoC) based Built-In-Self Test (BIST) architecture is an acceptable solution for testing embedded memory cores in Systems-On-Chip. The reuse of the available on-chip network to act as Test Access Mechnism brings down the area overhead as well as reduces test power. However, reducing the time to test still remains a problem due to latency in transporting the test instruction from BIST circuit to the memory cores. We have proposed a NoC based test architecture where a number of BIST controllers are shared by memory cores. A Particle Swarm Optimization (PSO) based technique is used (i) to place the BIST controllers at fixed locations and (ii) to form clusters of memories sharing the BIST controllers. This reduces the test instruction transport latency which in turn reduces the total test time of memory cores. Experimental results on different sizes of mesh based NoC confirm the effectiveness of our PSO based approach over heuristic techniques reported in literature as well as used in the industry.

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References

  1. 1.
    Marinissen, E.J., Prince, B., Keltel-Schulz, D., Zorian, Y.: Challenges in embedded memory design and test. In: Proceedings, Design, Automation and Test in Europe (DATE), vol. 2, pp. 722–727 (March 2005)Google Scholar
  2. 2.
    Bushnell, M.L., Agrawal, V.D.: Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. In: Frontiers in Electronic Testing. Kluwer Academic (2000)Google Scholar
  3. 3.
    Chien, T.-F., Chao, W.-C., Li, C.-M., Chang, Y.-W., Liao, K.-Y., Chang, M.-T., Tsai, M.-H., Tseng, C.-M.: Bist design optimization for large-scale embedded memory cores. In: Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 197–200 (November 2009)Google Scholar
  4. 4.
    Huang, Y.-J., Li, J.-F.: A low-cost pipelined bist scheme for homogeneous rams in multicore chips. In: Proceedings, 17th Asian Test Symposium (ATS), pp. 357–362 (November 2008)Google Scholar
  5. 5.
    Denq, L.-M., Wu, C.-W.: A hybrid bist scheme for multiple heterogeneous embedded memories. In: Proceedings, 16th Asian Test Symposium (ATS), pp. 349–354 (October 2007)Google Scholar
  6. 6.
    Miyazaki, M., Yoneda, T., Fujiwara, H.: A memory grouping method for sharing memory bist logic. In: Proceedings, Asia and South Pacific Conference on Design Automation, p. 6 (January 2006)Google Scholar
  7. 7.
    Liu, H.-N., Huang, Y.-J., Li, J.-F.: Memory built-in self test in multicore chips with mesh-based networks. IEEE Micro 29(5), 46–55 (2009)CrossRefGoogle Scholar
  8. 8.
    Guner, A.R., Sevkli, M.: A discrete particle swarm optimization algorithm for uncapacitated facility location problem. J. Artif. Evol. App. 2008, 10:1–10:9 (2008)CrossRefGoogle Scholar
  9. 9.
    Kennedy, J., Eberhart, R.: Particle swarm optimization. In: Proceedings, IEEE International Conference on Neural Networks, vol. 4, pp. 1942–1948 (November 1995)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Bibhas Ghoshal
    • 1
  • Subhadip Kundu
    • 1
  • Indranil Sengupta
    • 1
  • Santanu Chattopadhyay
    • 2
  1. 1.Department of Computer Science and EngineeringIndian Institute of Technology, KharagpurKharagpurIndia
  2. 2.Department of Electronics and Electrical Communication EngineeringIndian Institute of Technology, KharagpurKharagpurIndia

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