Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip

  • Bibhas Ghoshal
  • Subhadip Kundu
  • Indranil Sengupta
  • Santanu Chattopadhyay
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7373)


Network-on-Chip (NoC) based Built-In-Self Test (BIST) architecture is an acceptable solution for testing embedded memory cores in Systems-On-Chip. The reuse of the available on-chip network to act as Test Access Mechnism brings down the area overhead as well as reduces test power. However, reducing the time to test still remains a problem due to latency in transporting the test instruction from BIST circuit to the memory cores. We have proposed a NoC based test architecture where a number of BIST controllers are shared by memory cores. A Particle Swarm Optimization (PSO) based technique is used (i) to place the BIST controllers at fixed locations and (ii) to form clusters of memories sharing the BIST controllers. This reduces the test instruction transport latency which in turn reduces the total test time of memory cores. Experimental results on different sizes of mesh based NoC confirm the effectiveness of our PSO based approach over heuristic techniques reported in literature as well as used in the industry.


Particle Swarm Optimization Area Overhead Memory Core Uncapacitated Facility Location Problem Test Architecture 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Bibhas Ghoshal
    • 1
  • Subhadip Kundu
    • 1
  • Indranil Sengupta
    • 1
  • Santanu Chattopadhyay
    • 2
  1. 1.Department of Computer Science and EngineeringIndian Institute of Technology, KharagpurKharagpurIndia
  2. 2.Department of Electronics and Electrical Communication EngineeringIndian Institute of Technology, KharagpurKharagpurIndia

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