An Axiomatic Memory Model for POWER Multiprocessors

  • Sela Mador-Haim
  • Luc Maranget
  • Susmit Sarkar
  • Kayvan Memarian
  • Jade Alglave
  • Scott Owens
  • Rajeev Alur
  • Milo M. K. Martin
  • Peter Sewell
  • Derek Williams
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7358)

Abstract

The growing complexity of hardware optimizations employed by multiprocessors leads to subtle distinctions among allowed and disallowed behaviors, posing challenges in specifying their memory models formally and accurately, and in understanding and analyzing the behavior of concurrent software. This complexity is particularly evident in the IBM® Power Architecture®, for which a faithful specification was published only in 2011 using an operational style. In this paper we present an equivalent axiomatic specification, which is more abstract and concise. Although not officially sanctioned by the vendor, our results indicate that this axiomatic specification provides a reasonable basis for reasoning about current IBM® POWER® multiprocessors. We establish the equivalence of the axiomatic and operational specifications using both manual proof and extensive testing. To demonstrate that the constraint-based style of axiomatic specification is more amenable to computer-aided verification, we develop a SAT-based tool for evaluating possible outcomes of multi-threaded test programs, and we show that this tool is significantly more efficient than a tool based on an operational specification.

Keywords

Memory Model Control Dependency Conditional Branch Program Order Storage Subsystem 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [AAS03]
    Adir, A., Attiya, H., Shurek, G.: Information-flow models for shared memory with an application to the PowerPC architecture. IEEE Trans. Parallel Distrib. Syst. 14(5) (2003)Google Scholar
  2. [AFI+09]
    Alglave, J., Fox, A., Ishtiaq, S., Myreen, M.O., Sarkar, S., Sewell, P., Zappa Nardelli, F.: The semantics of Power and ARM multiprocessor machine code. In: Workshop on Declarative Aspects of Multicore Programming (January 2009)Google Scholar
  3. [AMSS10]
    Alglave, J., Maranget, L., Sarkar, S., Sewell, P.: Fences in Weak Memory Models. In: Touili, T., Cook, B., Jackson, P. (eds.) CAV 2010. LNCS, vol. 6174, pp. 258–272. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  4. [AMSS11]
    Alglave, J., Maranget, L., Sarkar, S., Sewell, P.: Litmus: Running Tests against Hardware. In: Abdulla, P.A., Leino, K.R.M. (eds.) TACAS 2011. LNCS, vol. 6605, pp. 41–44. Springer, Heidelberg (2011)CrossRefGoogle Scholar
  5. [CSB93]
    Corella, F., Stone, J.M., Barton, C.M.: A formal specification of the PowerPC shared memory architecture. Technical Report RC18638, IBM (1993)Google Scholar
  6. [ES05]
    Een, N., Sorensson, N.: Minisat - a SAT solver with conflict-clause minimization. In: International Conference on Theory and Applications of Satisfiability Testing (2005)Google Scholar
  7. [Gha95]
    Gharachorloo, K.: Memory consistency models for shared-memory multiprocessors. WRL Research Report 95(9) (1995)Google Scholar
  8. [Int02]
    Intel. A formal specification of Intel Itanium processor family memory ordering (2002), http://developer.intel.com/design/itanium/downloads/251429.html
  9. [OBZNS11]
    Owens, S., Böhm, P., Zappa Nardelli, F., Sewell, P.: Lem: A Lightweight Tool for Heavyweight Semantics. In: van Eekelen, M., Geuvers, H., Schmaltz, J., Wiedijk, F. (eds.) ITP 2011. LNCS, vol. 6898, pp. 363–369. Springer, Heidelberg (2011)CrossRefGoogle Scholar
  10. [SF95]
    Stone, J.M., Fitzgerald, R.P.: Storage in the PowerPC. IEEE Micro 15 (April 1995)Google Scholar
  11. [SMO+12]
    Sarkar, S., Memarian, K., Owens, S., Batty, M., Sewell, P., Maranget, L., Alglave, J., Williams, D.: Synchronising C/C++ and POWER. In: Programming Language Design and Implementation (2012)Google Scholar
  12. [SSA+11]
    Sarkar, S., Sewell, P., Alglave, J., Maranget, L., Williams, D.: Understanding POWER multiprocessors. In: Programming Language Design and Implementation (2011)Google Scholar
  13. [Sup]
    An axiomatic memory model for Power multiprocessors — supplementary material, http://www.seas.upenn.edu/~selama/axiompower.html
  14. [YGLS03]
    Yang, Y., Gopalakrishnan, G.C., Lindstrom, G., Slind, K.: Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT. In: Geist, D., Tronci, E. (eds.) CHARME 2003. LNCS, vol. 2860, pp. 81–95. Springer, Heidelberg (2003)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Sela Mador-Haim
    • 1
  • Luc Maranget
    • 2
  • Susmit Sarkar
    • 3
  • Kayvan Memarian
    • 3
  • Jade Alglave
    • 4
  • Scott Owens
    • 3
  • Rajeev Alur
    • 1
  • Milo M. K. Martin
    • 1
  • Peter Sewell
    • 3
  • Derek Williams
    • 5
  1. 1.University of PennsylvaniaUSA
  2. 2.INRIA Rocquencourt-ParisFrance
  3. 3.University of CambridgeUSA
  4. 4.University of OxfordUSA
  5. 5.IBMAustinUSA

Personalised recommendations