A Small Depth-16 Circuit for the AES S-Box

  • Joan Boyar
  • René Peralta
Part of the IFIP Advances in Information and Communication Technology book series (IFIPAICT, volume 376)


New techniques for reducing the depth of circuits for cryptographic applications are described. These techniques also keep the number of gates quite small. The result, when applied to the AES S-Box, is a circuit with depth 16 and only 128 gates. For the inverse, it is also depth 16 and has only 127 gates. There is a shared middle part, common to both the S-Box and its inverse, consisting of 63 gates. The best previous comparable design for the AES S-Box has depth 22 and size 148 [12].


Advance Encryption Standard Linear Component Greedy Heuristic Nonlinear Component Combinational Circuit 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© IFIP International Federation for Information Processing 2012

Authors and Affiliations

  • Joan Boyar
    • 1
  • René Peralta
    • 2
  1. 1.Department of Mathematics and Computer ScienceUniversity of Southern DenmarkDenmark
  2. 2.Information Technology LaboratoryNISTUSA

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