Enabling Next-Generation Parallel Circuit Simulation with Trilinos

  • Chris Baker
  • Erik Boman
  • Mike Heroux
  • Eric Keiter
  • Siva Rajamanickam
  • Rich Schiek
  • Heidi Thornquist
Conference paper

DOI: 10.1007/978-3-642-29737-3_36

Part of the Lecture Notes in Computer Science book series (LNCS, volume 7155)
Cite this paper as:
Baker C. et al. (2012) Enabling Next-Generation Parallel Circuit Simulation with Trilinos. In: Alexander M. et al. (eds) Euro-Par 2011: Parallel Processing Workshops. Euro-Par 2011. Lecture Notes in Computer Science, vol 7155. Springer, Berlin, Heidelberg

Abstract

The Xyce Parallel Circuit Simulator, which has demonstrated scalable circuit simulation on hundreds of processors, heavily leverages the high-performance scientific libraries provided by Trilinos. With the move towards multi-core CPUs and GPU technology, retaining this scalability on future parallel architectures will be a challenge. This paper will discuss how Trilinos is an enabling technology that will optimize the trade-off between effort and impact for application codes, like Xyce, in their transition to becoming next-generation simulation tools.

Keywords

circuit simulation parallel computing hybrid computing preconditioned iterative methods load balancing 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Chris Baker
    • 1
  • Erik Boman
    • 2
  • Mike Heroux
    • 2
  • Eric Keiter
    • 2
  • Siva Rajamanickam
    • 2
  • Rich Schiek
    • 2
  • Heidi Thornquist
    • 2
  1. 1.Oak Ridge National LaboratoryOak RidgeUSA
  2. 2.Sandia National LaboratoriesAlbuquerqueUSA

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