Counter-Example Guided Fence Insertion under TSO

  • Parosh Aziz Abdulla
  • Mohamed Faouzi Atig
  • Yu-Fang Chen
  • Carl Leonardsson
  • Ahmed Rezine
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7214)


We give a sound and complete fence insertion procedure for concurrent finite-state programs running under the classical TSO memory model. This model allows “write to read” relaxation corresponding to the addition of an unbounded store buffer between each processor and the main memory. We introduce a novel machine model, called the Single-Buffer (SB) semantics, and show that the reachability problem for a program under TSO can be reduced to the reachability problem under SB. We present a simple and effective backward reachability analysis algorithm for the latter, and propose a counter-example guided fence insertion procedure. The procedure is augmented by a placement constraint that allows the user to choose places inside the program where fences may be inserted. For a given placement constraint, we automatically infer all minimal sets of fences that ensure correctness. We have implemented a prototype and run it successfully on all standard benchmarks together with several challenging examples that are beyond the applicability of existing methods.


Memory Model Mutual Exclusion Read Operation Reachability Problem Bound Model Check 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


  1. 1.
    Abdulla, P.A., Cerans, K., Jonsson, B., Tsay, Y.-K.: General decidability theorems for infinite-state systems. In: LICS (1996)Google Scholar
  2. 2.
    Adve, S., Gharachorloo, K.: Shared memory consistency models: a tutorial. Computer 29(12) (1996)Google Scholar
  3. 3.
    Alglave, J., Maranget, L.: Stability in Weak Memory Models. In: Gopalakrishnan, G., Qadeer, S. (eds.) CAV 2011. LNCS, vol. 6806, pp. 50–66. Springer, Heidelberg (2011)CrossRefGoogle Scholar
  4. 4.
    Atig, M.F., Bouajjani, A., Burckhardt, S., Musuvathi, M.: On the verification problem for weak memory models. In: POPL (2010)Google Scholar
  5. 5.
    Atig, M.F., Bouajjani, A., Parlato, G.: Getting Rid of Store-Buffers in TSO Analysis. In: Gopalakrishnan, G., Qadeer, S. (eds.) CAV 2011. LNCS, vol. 6806, pp. 99–115. Springer, Heidelberg (2011)CrossRefGoogle Scholar
  6. 6.
    Burckhardt, S., Alur, R., Martin, M.: CheckFence: Checking consistency of concurrent data types on relaxed memory models. In: PLDI (2007)Google Scholar
  7. 7.
    Burckhardt, S., Alur, R., Martin, M.M.K.: Bounded Model Checking of Concurrent Data Types on Relaxed Memory Models: A Case Study. In: Ball, T., Jones, R.B. (eds.) CAV 2006. LNCS, vol. 4144, pp. 489–502. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  8. 8.
    Burckhardt, S., Musuvathi, M.: Effective Program Verification for Relaxed Memory Models. In: Gupta, A., Malik, S. (eds.) CAV 2008. LNCS, vol. 5123, pp. 107–120. Springer, Heidelberg (2008)CrossRefGoogle Scholar
  9. 9.
    Burnim, J., Sen, K., Stergiou, C.: Testing concurrent programs on relaxed memory models. Technical Report UCB/EECS-2010-32, UCB (2010)Google Scholar
  10. 10.
    Burnim, J., Sen, K., Stergiou, C.: Sound and Complete Monitoring of Sequential Consistency for Relaxed Memory Models. In: Abdulla, P.A., Leino, K.R.M. (eds.) TACAS 2011. LNCS, vol. 6605, pp. 11–25. Springer, Heidelberg (2011)CrossRefGoogle Scholar
  11. 11.
    Dijkstra, E.W.: Cooperating sequential processes. Springer-Verlag New York, Inc., New York (2002)Google Scholar
  12. 12.
    Fang, X., Lee, J., Midkiff, S.P.: Automatic fence insertion for shared memory multiprocessing. In: ICS. ACM (2003)Google Scholar
  13. 13.
    Fraser, K.: Practical lock-freedom. Technical Report UCAM-CL-TR-579, University of Cambridge, Computer Laboratory (2004)Google Scholar
  14. 14.
    Hensgen, D., Finkel, R., Manber, U.: Two algorithms for barrier synchronization. IJPP 17 (February 1988)Google Scholar
  15. 15.
    Higman, G.: Ordering by divisibility in abstract algebras. Proc. London Math. Soc. (3), 2(7) (1952)Google Scholar
  16. 16.
    Huynh, T.Q., Roychoudhury, A.: A Memory Model Sensitive Checker for C#. In: Misra, J., Nipkow, T., Karakostas, G. (eds.) FM 2006. LNCS, vol. 4085, pp. 476–491. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  17. 17.
    I. Inc. IntelTM64 and IA-32 Architectures Software Developer’s ManualsGoogle Scholar
  18. 18.
    Kuperstein, M., Vechev, M., Yahav, E.: Automatic inference of memory fences. In: FMCAD (2011)Google Scholar
  19. 19.
    Kuperstein, M., Vechev, M., Yahav, E.: Partial-coherence abstractions for relaxed memory models. In: PLDI (2011)Google Scholar
  20. 20.
    Lamport, L.: A new solution of dijkstra’s concurrent programming problem. CACM 17 (August 1974)Google Scholar
  21. 21.
    Lamport, L.: A fast mutual exclusion algorithm (1986)Google Scholar
  22. 22.
    Linden, A., Wolper, P.: An Automata-Based Symbolic Approach for Verifying Programs on Relaxed Memory Models. In: van de Pol, J., Weber, M. (eds.) SPIN 2010. LNCS, vol. 6349, pp. 212–226. Springer, Heidelberg (2010)Google Scholar
  23. 23.
    Linden, A., Wolper, P.: A Verification-Based Approach to Memory Fence Insertion in Relaxed Memory Systems. In: Groce, A., Musuvathi, M. (eds.) SPIN 2011. LNCS, vol. 6823, pp. 144–160. Springer, Heidelberg (2011)Google Scholar
  24. 24.
    Lynch, N., Patt-Shamir, B.: Distributed Algorithms, Lecture Notes for 6.852 FALL 1992. Technical report, MIT, Cambridge, MA, USA (1993)Google Scholar
  25. 25.
    Magnusson, P., Landin, A., Hagersten, E.: Queue locks on cache coherent multiprocessors. In: IPPS. IEEE Computer Society (1994)Google Scholar
  26. 26.
    Mellor-Crummey, J.M., Scott, M.L.: Algorithms for scalable synchronization on shared-memory multiprocessors. ACM Trans. Comput. Syst. 9 (February 1991)Google Scholar
  27. 27.
    Owens, S.: Reasoning about the Implementation of Concurrency Abstractions on x86-TSO. In: D’Hondt, T. (ed.) ECOOP 2010. LNCS, vol. 6183, pp. 478–503. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  28. 28.
    Owens, S., Sarkar, S., Sewell, P.: A Better x86 Memory Model: x86-TSO. In: Berghofer, S., Nipkow, T., Urban, C., Wenzel, M. (eds.) TPHOLs 2009. LNCS, vol. 5674, pp. 391–407. Springer, Heidelberg (2009)CrossRefGoogle Scholar
  29. 29.
    Peterson, G.L.: Myths About the Mutual Exclusion Problem. IPL 12(3) (1981)Google Scholar
  30. 30.
    Sewell, P., Sarkar, S., Owens, S., Nardelli, F.Z., Myreen, M.O.: x86-tso: A rigorous and usable programmer’s model for x86 multiprocessors. CACM 53 (2010)Google Scholar
  31. 31.
    Weaver, D., Germond, T. (eds.): The SPARC Architecture Manual Version 9. PTR Prentice Hall (1994)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Parosh Aziz Abdulla
    • 1
  • Mohamed Faouzi Atig
    • 1
  • Yu-Fang Chen
    • 2
  • Carl Leonardsson
    • 1
  • Ahmed Rezine
    • 3
  1. 1.Uppsala UniversitySweden
  2. 2.Academia SinicaTaiwan
  3. 3.Linköping UniversitySweden

Personalised recommendations