Abstract

Modern three-dimensional (3D) designs, in which the active devices are placed in multiple layers using 3D integration technologies, are helping to maintain the validity of Moore’s law in today’s nano era. In this chapter, an overview of technologies and physical design in the new 3-dimensional context is presented. A survey of modern 3D integration technologies, such as 3D packages and 3D integrated circuits, is given first. The author then investigates the physical design steps of floorplanning, placement and routing to identify the new design challenges and solutions of 3D nanoscale circuits.

Keywords

Physical Design Wafer Level Total Wire Length Circuit Layer Routability Prediction 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Notes

Acknowledgments

The author would like to thank Robert Fischbach and Tilo Meister for their contributions to this work.

References

  1. 1.
    Beyne, E.: The rise of the 3rd dimension for system integration. In: International Interconnect Technology Conference, pp. 1–5, San Francisco, USA, July 2006Google Scholar
  2. 2.
    Cheng, L., Deng, L., Wong, M.D.F.: Floorplanning for 3-D VLSI design. In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC ’05, pp. 405–411. ACM (2005). doi:10.1145/1120725.1120899Google Scholar
  3. 3.
    Cong, J., Wei, J., Zhang, Y.: A thermal-driven floorplanning algorithm for 3D ICs. In: IEEE/ACM International Conference on Computer Aided Design, ICCAD-2004, pp. 306–313. (2004)Google Scholar
  4. 4.
    Cong, J., Zhang, Y.: Thermal-driven multilevel routing for 3D ICs. In: Proceedings of the 2005 Conference on Asia and South Pacific Design Automation, ASP-DAC 2005, vol. 1, pp. 121–126. ACM (2005). doi: 10.1109/ASPDAC.2005.1466143Google Scholar
  5. 5.
    Das, S.: Design automation and analysis of three-dimensional integrated circuits. Ph.D. thesis, Massachusetts Institute of Technology (2004)Google Scholar
  6. 6.
    Das, S., Chandrakasan, A., Reif, R.: Design tools for 3-D integrated circuits. In: Proceedings of the 2003 Conference on Asia and South Pacific Design Automation, ASP-DAC 2003, pp. 53–56. doi:10.1109/ASPDAC.2003.1194993Google Scholar
  7. 7.
    Davis, W.R., Wilson, J., Mick, S., Xu, J., Hua, H., Mineo, C., Sule, A.M., Steer, M., Franzon, P.D.: Demystifying 3D ICs: the pros and cons of going vertical. IEEE Des. Test Comput. 22(6), 498–510 (2005). doi: 10.1109/MDT.2005.136 CrossRefGoogle Scholar
  8. 8.
    Fischbach, R., Lienig, J., Meister, T.: From 3D circuit technologies and data structures to interconnect prediction. In: SLIP ’09: Proceedings of the 11th International Workshop on System Level Interconnect Prediction, pp. 77–84. ACM, New York (2009). doi:10.1145/1572471.1572485.Google Scholar
  9. 9.
    Goplen, B., Sapatnekar, S.: Efficient thermal placement of standard cells in 3D ICs using a force directed approach. In: International Conference on Computer Aided Design, ICCAD-2003, pp. 86–89 (2003)Google Scholar
  10. 10.
    Goplen, B., Sapatnekar, S.: Thermal via placement in 3D ICs. In: Proceedings of the 2005 International Symposium on Physical Design, ISPD ’05, pp. 167–174. ACM, New York (2005). doi: 10.1145/1055137.1055171Google Scholar
  11. 11.
    Goplen, B., Sapatnekar, S.: Placement of 3D ICs with thermal and interlayer via considerations. In: S. Sapatnekar (ed.) Proceedings of the 44th ACM/IEEE Design Automation Conference DAC ’07, pp. 626–631 (2007). doi: 10.1109/DAC.2007.375239Google Scholar
  12. 12.
    Guarini, K.W., Topol, A.W., Ieong, M., et al.: Electrical integrity of state-of-the-art 0.13 mum SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication. In: Proceedings of the Digest. International Electron Devices Meeting IEDM ’02, pp. 943–945 (2002). doi:10.1109/IEDM.2002.1175992Google Scholar
  13. 13.
    ITRS: International Technology Roadmap for Semiconductors. Tech. rep., ESIA, JEITA, KSIA, TSIA and SIA (2007). http://www.itrs.net/reports.html
  14. 14.
    Knechtel, J., Markov, I.L., Lienig, J.: Assembling 2D blocks into 3D chips. In: Proceedings of the 2011 International Symposium on Physical Design, pp. 81–88. ACM (2011). doi: 10.1109.TCAD.2011.2174640
  15. 15.
    Lim, S.K.: Physical design for 3D system on package. IEEE Des. Test Comput. 22(6), 532–539 (2005). doi: 10.1109/MDT.2005.149 CrossRefGoogle Scholar
  16. 16.
    Loh, G.H., Xie, Y., Black, B.: Processor design in 3D die-stacking technologies. IEEE Micro. 27(3), 31–48 (2007). doi: 10.1109/MM.2007.59 CrossRefGoogle Scholar
  17. 17.
    Lou, J., Krishnamoorthy, S., Sheng, H.S.: Estimating routing congestion using probabilistic analysis. In: Proceedings of the 2001 International Symposium on Physical Design, ISPD ’01, pp. 112–117. ACM (2001). doi:10.1145/369691.369749Google Scholar
  18. 18.
    Topol, A.W., Tulipe Jr, D.C., Shi, L., Frank, D.J., Bernstein, K., Steen, S.E., Kumar, A., Singco, G.U., Young, A.M., Guarini, K.W., Ieong, M.: Three-dimensional integrated circuits. IBM J. Res. Dev. 50(4/5), 491–506 (2006). doi: 10.1147/rd.504.0491 CrossRefGoogle Scholar
  19. 19.
    Tummala, R.R.: SOP: What is it and why? A new microsystem-integration technology paradigm-moore’s law for system integration of miniaturized convergent systems of the next decade. IEEE Trans. Adv. Pack. 27(2), 241–249 (2004). doi: 10.1109/TADVP.2004.830354 CrossRefGoogle Scholar
  20. 20.
    Viswanathan, N., Chu, C.C.N.: FastPlace: efficient analytical placement using cell shifting, iterative local refinement, and a hybrid net model. IEEE Trans. Comput. Aid. D. 24(5), 722–733 (2005). doi: 10.1109/TCAD.2005.846365 CrossRefGoogle Scholar
  21. 21.
    Xie, Y., Loh, G.H., Black, B., Bernstein, K.: Design space exploration for 3D architectures. J. Emerg. Technol. Comput. Syst. 2(2), 65–103 (2006). doi:10.1145/1148015.1148016Google Scholar
  22. 22.
    Zhang, T., Zhan, Y., Sapatnekar, S.S.: Temperature-aware routing in 3D ICs. In: Asia and South Pacific Conference on Design Automation, 2006, pp. 309–314. doi:10.1109/ASPDAC.2006.1594700Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  1. 1.Institute of Electromechanical and Electronic DesignTechnische Universität DresdenDresdenGermany

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