Table-Based Division by Small Integer Constants

  • Florent de Dinechin
  • Laurent-Stéphane Didier
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7199)


Computing cores to be implemented on FPGAs may involve divisions by small integer constants in fixed or floating point. This article presents a family of architectures addressing this need. They are derived from a simple recurrence whose body can be implemented very efficiently as a look-up table that matches the hardware resources of the target FPGA. For instance, division of a 32-bit integer by the constant 3 may be implemented by a combinatorial circuit of 48 LUT6 on a Virtex-5. Other options are studied, including iterative implementations, and architectures based on embedded memory blocks. This technique also computes the remainder. An efficient implementation of the correctly rounded division of a floating-point constant by such a small integer is also presented.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2012

Authors and Affiliations

  • Florent de Dinechin
    • 1
  • Laurent-Stéphane Didier
    • 2
  1. 1.LIPUniversité de Lyon (ENS-Lyon/CNRS/INRIA/UCBL)Lyon Cedex 07France
  2. 2.LIP6Université Pierre et Marie Curie (UPMC/CNRS)Paris Cedex 05France

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