AER Spiking Neuron Computation on GPUs: The Frame-to-AER Generation

  • M. R. López-Torres
  • F. Diaz-del-Rio
  • M. Domínguez-Morales
  • G. Jimenez-Moreno
  • A. Linares-Barranco
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7062)


Neuro-inspired processing tries to imitate the nervous system and may resolve complex problems, such as visual recognition. The spike-based philosophy based on the Address-Event-Representation (AER) is a neuromorphic interchip communication protocol that allows for massive connectivity between neurons. Some of the AER-based systems can achieve very high performances in real-time applications. This philosophy is very different from standard image processing, which considers the visual information as a succession of frames. These frames need to be processed in order to extract a result. This usually requires very expensive operations and high computing resource consumption. Due to its relative youth, nowadays AER systems are short of cost-effective tools like emulators, simulators, testers, debuggers, etc. In this paper the first results of a CUDA-based tool focused on the functional processing of AER spikes is presented, with the aim of helping in the design and testing of filters and buses management of these systems.


AER neuromorphic CUDA GPUs real-time vision spiking systems 


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  1. 1.
    Drubach, D.: The Brain Explained. Prentice-Hall, New Jersey (2000)Google Scholar
  2. 2.
    Lee, J.: A Simple Speckle Smoothing Algorithm for Synthetic Aperture Radar Images. IEEE Trans. Systems, Man and Cybernetics  SMC-13, 85–89 (1983)CrossRefGoogle Scholar
  3. 3.
    Crimmins, T.: Geometric Filter for Speckle Reduction. Applied Optics 24 (1985)Google Scholar
  4. 4.
    Linares-Barranco, A., et al.: On the AER Convolution Processors for FPGA. In: ISCAS 2010, Paris, France (2010)Google Scholar
  5. 5.
    Sivilotti, M.: Wiring Considerations in analog VLSI Systems with Application to Field-Programmable Networks, Ph.D. Thesis, California Institute of Technology (1991)Google Scholar
  6. 6.
    Boahen, K.A.: Communicating Neuronal Ensembles between Neuromorphic Chips. In: Neuromorphic Systems. Kluwer Academic Publishers, Boston (1998)Google Scholar
  7. 7.
    Mahowald, M.: VLSI Analogs of Neuronal Visual Processing: A Synthesis of Form and Function. Ph.D. Thesis. California Institute of Technology Pasadena, California (1992)Google Scholar
  8. 8.
    Linares-Barranco, A., Jimenez-Moreno, G., Civit-Ballcels, A., Linares-Barranco, B.: On Algorithmic Rate-Coded AER Generation. IEEE Transaction on Neural Networks (2006)Google Scholar
  9. 9.
    Paz, R., Gomez-Rodriguez, F., Rodríguez, M.A., Linares-Barranco, A., Jimenez, G., Civit, A.: Test Infrastructure for Address-Event-Representation Communications. In: Cabestany, J., Prieto, A.G., Sandoval, F. (eds.) IWANN 2005. LNCS, vol. 3512, pp. 518–526. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  10. 10.
    Serrano, et al.: A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vission Systems. IEEE Trans. on Circuits and Systems Part 1 53(12), 2548–2566 (2006)Google Scholar
  11. 11.
    Cope, B., Cheung, P.Y.K., Luk, W., Witt, S.: Have GPUs made FPGAs redundant in the field of video processing? In: IEEE International Conference on Field-Programmable Technology, pp. 111–118 (2005)Google Scholar
  12. 12.
    Farabet, C., et al.: CNP: An FPGA-based Processor for Convolutional Networks. In: International Conference on Field Programmable Logic and Applications (2009)Google Scholar
  13. 13.
    Farriga, N., et al.: Design of a Real-Time Face Detection Parallel Architecture Using High-Level Synthesis. EURASIP Journal on Embedded Systems (2008)Google Scholar
  14. 14.
    Domínguez-Morales, M., et al.: Performance study of synthetic AER generation on CPUs for Real-Time Video based on Spikes. In: SPECTS 2009, Istambul, Turkey (2009)Google Scholar
  15. 15.
    Nageswaran, J.M., Dutt, N., Wang, Y., Delbrueck, T.: Computing spike-based convolutions on GPUs. In: IEEE International Symposium on Circuits and Systems (ISCAS 2009), Taipei, Taiwan, pp. 1917–1920 (2009)Google Scholar
  16. 16.
    Goodman, D.: Code Generation: A Strategy for Neural Network Simulators. Neuroinformatics 8.3, 183–196 (2010), Issn: 1539-2791CrossRefGoogle Scholar
  17. 17.
    Compute Visual Profiler User Guide,
  18. 18.
    NVIDIA CUDA Programming Guide, Version 2.1,
  19. 19.
    NVIDIA Corporation. CUDA SDK Software development kit,
  20. 20.
    Paz-Vicente, R., et al.: Synthetic retina for AER systems development. In: IEEE/ACS International Conference on Computer Systems and Applications, AICCSA, pp. 907–912 (2009)Google Scholar
  21. 21.
    Owens, J.D., Houston, M., Luebke, D., Green, S., Stone, J.E., Phillips, J.C.: GPU Computing. Proceedings of the IEEE 96(5) (May 2008)Google Scholar
  22. 22.
    Indiveri, G., et al.: Neuromorphic Silicon Neurons. Frontiers in Neuromorphic Engineering 5, 7 (2011)Google Scholar
  23. 23.
    Halfhill, T.R.: Parallel Processing With CUDA. Microprocessor The Insider’s Guide To Microprocessor Hardware (2008)Google Scholar
  24. 24.
    Thorpe, S., et al.: Spike-based strategies for rapid processing. Neural Networks 14(6-7), 715–725 (2001)CrossRefGoogle Scholar
  25. 25.
    Pérez-Carrasco, J.-A., Serrano-Gotarredona, C., Acha-Piñero, B., Serrano-Gotarredona, T., Linares-Barranco, B.: Advanced Vision Processing Systems: Spike-Based Simulation and Processing. In: Blanc-Talon, J., Philips, W., Popescu, D., Scheunders, P. (eds.) ACIVS 2009. LNCS, vol. 5807, pp. 640–651. Springer, Heidelberg (2009)CrossRefGoogle Scholar
  26. 26.
    Montero-Gonzalez, R.J., Morgado-Estevez, A., Linares-Barranco, A., Linares-Barranco, B., Perez-Peña, F., Perez-Carrasco, J.A., Jimenez-Fernandez, A.: Performance Study of Software AER-Based Convolutions on a Parallel Supercomputer. In: Cabestany, J., Rojas, I., Joya, G. (eds.) IWANN 2011, Part I. LNCS, vol. 6691, pp. 141–148. Springer, Heidelberg (2011)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • M. R. López-Torres
    • 1
  • F. Diaz-del-Rio
    • 1
  • M. Domínguez-Morales
    • 1
  • G. Jimenez-Moreno
    • 1
  • A. Linares-Barranco
    • 1
  1. 1.Department of Architecture and Technology of ComputersUniversity of SevilleSpain

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