LUTS: A Lightweight User-Level Transaction Scheduler

  • Daniel Nicácio
  • Alexandro Baldassin
  • Guido Araújo
Part of the Lecture Notes in Computer Science book series (LNCS, volume 7016)


Software Transactional Memory (STM) systems have poor performance under high contention scenarios. Since many transactions compete for the same data, most of them are aborted, wasting processor runtime. Contention management policies are typically used to avoid that, but they are passive approaches as they wait for an abort to happen so they can take action. More proactive approaches have emerged, trying to predict when a transaction is likely to abort so its execution can be delayed. Such techniques are limited, as they do not replace the doomed transaction by another or, when they do, they rely on the operating system for that, having little or no control on which transaction should run. In this paper we propose LUTS, a Lightweight User-Level Transaction Scheduler, which is based on an execution context record mechanism. Unlike other techniques, LUTS provides the means for selecting another transaction to run in parallel, thus improving system throughput. Moreover, it avoids most of the issues caused by pseudo parallelism, as it only launches as many system-level threads as the number of available processor cores. We discuss LUTS design and present three conflict-avoidance heuristics built around LUTS scheduling capabilities. Experimental results, conducted with STMBench7 and STAMP benchmark suites, show LUTS efficiency when running high contention applications and how conflict-avoidance heuristics can improve STM performance even more. In fact, our transaction scheduling techniques are capable of improving program performance even in overloaded scenarios.


Processor Core Transactional Memory Active Vector Active Transaction Atomic Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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  1. 1.
    Harris, T., Larus, J., Rajwar, R.: Transactional Memory, 2nd edn. Morgan & Claypool Publishers (June 2010)Google Scholar
  2. 2.
    Guerraoui, R., Herlihy, M., Pochon, B.: Toward a theory of transactional contention managers. In: PODC 2005, pp. 258–264 (July 2005)Google Scholar
  3. 3.
    Dolev, S., Hendler, D., Suissa, A.: CAR-STM: Scheduling-based collision avoidance and resolution for software transactional memory. In: PODC 2008, pp. 125–134 (August 2008)Google Scholar
  4. 4.
    Guerraoui, R., Kapalka, M., Vitek, J.: STMBench7: A benchmark for software transactional memory. In: EUROSYS 2007, pp. 315–324 (March 2007)Google Scholar
  5. 5.
    Minh, C.C., Chung, J., Kozyrakis, C., Olukotun, K.: STAMP: Stanford transactional applications for multi-processing. In: IISWC, pp. 35–46 (September 2008)Google Scholar
  6. 6.
    Yoo, R.M., Lee, H.H.S.: Adaptive transaction scheduling for transactional memory systems. In: SPAA 2008, pp. 169–178 (June 2008)Google Scholar
  7. 7.
    Dragojevic, A., Guerraoui, R., Singh, A.V., Singh, V.: Preventing versus curing: Avoiding conflicts in transactional memories. In: PODC 2009, pp. 7–16 (August 2009)Google Scholar
  8. 8.
    Herlihy, M., Luchangco, V., Moir, M., Scherer, W.N.: Software transactional memory for dynamic-sized data structures. In: PODC 2003, pp. 92–101 (July 2003)Google Scholar
  9. 9.
    Scherer, W.N., Scott, M.L.: Advanced contention management for dynamic software transactional memory. In: PODC 2005, pp. 240–248 (July 2005)Google Scholar
  10. 10.
    Guerraoui, R., Herlihy, M., Pochon, B.: Polymorphic contention management. In: Fraigniaud, P. (ed.) DISC 2005. LNCS, vol. 3724, pp. 303–323. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  11. 11.
    Spear, M.F., Dalessandro, L., Marathe, V.J., Scott, M.L.: A comprehensive strategy for contention management in software transactional memory. In: PPoPP 2009, pp. 141–150 (February 2009)Google Scholar
  12. 12.
    Maldonado, W., Marlier, P., Felber, P., Suissa, A., Hendler, D., Fedorova, A., Lawall, J.L., Muller, G.: Scheduling support for transactional memory contention management. In: PPOPP 2010, pp. 79–90 (January 2010)Google Scholar
  13. 13.
    Ansari, M., Luján, M., Kotselidis, C., Jarvis, K., Kirkham, C., Watson, I.: Steal-on-Abort: Improving transactional memory performance through dynamic transaction reordering. In: Seznec, A., Emer, J., O’Boyle, M., Martonosi, M., Ungerer, T. (eds.) HiPEAC 2009. LNCS, vol. 5409, pp. 4–18. Springer, Heidelberg (2009)CrossRefGoogle Scholar
  14. 14.
    Blake, G., Dreslinski, R.G., Mudge, T.: Proactive transaction scheduling for contention management. In: MICRO 2009, pp. 156–167 (December 2009)Google Scholar
  15. 15.
    Anderson, T.E., Bershad, B.N., Lazowska, E.D., Levy, H.M.: Scheduler activations: effective kernel support for the user-level management of parallelism. SIGOPS Oper. Syst. Rev. 25, 95–109 (1991)CrossRefGoogle Scholar
  16. 16.
    Saha, B., Adl-Tabatabai, A.R., Hudson, R.L., Minh, C.C., Hertzberg, B.: Mcrt-stm: a high performance software transactional memory system for a multi-core runtime. In: PPoPP 2006, pp. 187–197. ACM, New York (2006)Google Scholar
  17. 17.
    Dragojevic, A., Guerraoui, R., Kapalka, M.: Stretching transactional memory. In: PLDI 2009, pp. 155–165 (June 2009)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Daniel Nicácio
    • 1
  • Alexandro Baldassin
    • 2
  • Guido Araújo
    • 1
  1. 1.IC-UNICAMPBrazil
  2. 2.UNESP - Univ Estadual PaulistaRio ClaroBrazil

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