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On Two-Layer Brain-Inspired Hierarchical Topologies – A Rent’s Rule Approach –

  • Valeriu Beiu
  • Basheer A. M. Madappuram
  • Peter M. Kelly
  • Liam J. McDaid
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6760)

Abstract

This research compares the brain’s connectivity (based on different analyses of neurological data) with well-known network topologies (originally used in super-computers) using Rent’s rule. The comparison reveals that brain connectivity is in good agreement with Rent’s rule. However, the known network topologies fall short of being strong contenders for mimicking brain’s connectivity. That is why we perform a detailed Rent-based (top-down) connectivity analysis of generic two-layer hierarchical network topologies. This analysis aims to identify generic two-layer hierarchical network topologies which could closely mimic brain’s connectivity. The range of granularities (i.e., number of gates/cores/neurons) where such mimicking is possible are identified and discussed. These results should have implications for the design of future networks-on-chip in general, and for the burgeoning field of multi/many-core processors in particular (in the medium term), as well as for forward-looking investigations on emerging brain-inspired nano-architectures (in the long run).

Keywords

Connectivity network topology network-on-chip communication nano-architecture Rent’s rule neural networks brain 

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References

  1. 1.
    International Technology Roadmap for Semiconductors (ITRS), 2007 Edition and 2008 Upadate, SEMATECH, Austin, TX, USA (2009), http://public.itrs.net/
  2. 2.
    Cavin, R.K., Zhirnov, V.V., Herr, D.C., Avila, A., Hutchby, J.: Research directions and challenges in nanoelectronics. J. Nanoparticle Res. 8, 841–858 (2006)CrossRefGoogle Scholar
  3. 3.
    Santo, B., Adee, S.: Multicore made simple. IEEE Spectrum 46, 32–36 (2009)CrossRefGoogle Scholar
  4. 4.
    Ye, T.T., De Micheli, G.: Physical planning for on-chip multiprocessor networks and switching fabrics. In: Proc. Intl. Conf. Appl.-Specific Syst. Arch. & Proc. (ASAP 2003), Hague, The Netherlands, June 24-26, pp. 97–107 (2003)Google Scholar
  5. 5.
    Beiu, V., Rückert, U., Roy, S., Nyathi, J.: On nanoelectronic architectural challenges and solutions. In: Proc. Intl. Conf. Nanotech. (IEEE-NANO 2004), Munich, Germany, August 17-19, pp. 628–631 (2004)Google Scholar
  6. 6.
    Reed, D.: Multicore: Let’s not focus on the present. Proc. Intl. Super Comp. Conf. (SC 2007), Reno, NV, USA, November 10-16 (2007), http://gamma.cs.unc.edu/SC2007/DanReedSlides.pdf
  7. 7.
    Asanovic, K., Bodik, R., Demmel, J., Keaveny, T., Keutzer, K., Kubiatowicz, J., Morgan, N., Patterson, D., Sen, K., Wawrzynek, J., Wessel, D., Yelick, K.: A view of the parallel computing landscape. Comm. ACM 52, 56–67 (2009)CrossRefGoogle Scholar
  8. 8.
    Kolodny, A.: Networks on Chip – Keeping up with Rent’s rule and Moore’s law. In: Proc. Intl. Workshop Syst.-Level Intercon. Predict (SLIP 2007), Austin, TX, USA, March 17-18, p. 55 (2007), http://www.sliponline.org/SLIP07/presentations/4A_Kolodny.pdf
  9. 9.
    Lee, H.G., Chang, N., Ogras, U.Y., Marculescu, R.: On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches. ACM Trans. Design Autom. Electr. Syst. 12, art. 23, 1–20 (2007)CrossRefGoogle Scholar
  10. 10.
    Wen, Q., Chklovskii, D.B.: Segregation of the brain into gray and white matter: A design minimizing conduction delays. PLoS Comp. Biol. 1, 617–630 (2005)CrossRefGoogle Scholar
  11. 11.
    Azevedo, F.A.C., Carvalho, L.R.B., Grinberg, L.T., Farfel, J.M., Ferretti, R.E.L., Leite, R.E.P., Jacob Filho, W., Lent, R., Herculano-Houzel, S.: Equal numbers of neuronal and nonneuronal cells make the human brain an isometrically scaled-up primate brain. J. Comp. Neurol. 513, 532–541 (2009)CrossRefGoogle Scholar
  12. 12.
    Jóźwiak, L.: Life-inspired systems and their quality-driven design (keynote paper). In: Grass, W., Sick, B., Waldschmidt, K. (eds.) ARCS 2006. LNCS, vol. 3894, pp. 1–16. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  13. 13.
    Wyss Institute for Biologically Inspired Engineering, http://wyss.harvard.edu/
  14. 14.
    Miller, D.A.B.: Optical for low-energy communication inside digital processors: Quantum detectors, sources, and modulators as efficient impedance converters. Optics Lett. 14, 146–148 (1989)CrossRefGoogle Scholar
  15. 15.
    Yablonovitch, E.: The impedance-matching predicament: A hurdle in the race toward nano-electronics. In: Center for NanoScience (CeNS) Workshop: Emerging Nanosystems – From Quantum Manipulations to Nanobiomachines, Venice, Italy, p. 20 (September 2006), http://www.cens.de/uploads/media/CeNS_proceedings06.pdf
  16. 16.
    Sakurai, T.: Design challenges for 0.1μm and beyond. In: Proc. Asia & South Pacific Design Autom. Conf. (ASP-DAC 2000), Tokyo, Japan, pp. 553–558 (January 2000)Google Scholar
  17. 17.
    Davis, J.A., Venkatesan, R., Kaloyeros, A., Beylansky, M., Souri, S.J., Banerjee, K., Saraswat, K.C., Rahman, A., Reif, R., Meindl, J.D.: Interconnect limits on gigascale integration (GSI) in the 21st century. Proc. IEEE 89, 305–324 (2001)CrossRefGoogle Scholar
  18. 18.
    Davis, J.A., Meindl, J.: Interconnect Technology and Design for Gigascale Integration. Kluwer, Dordrecht (2003)CrossRefzbMATHGoogle Scholar
  19. 19.
    Magen, N., Kolodny, A., Weiser, U., Shamir, N.: Interconnect-power dissipation in a microprocessor. In: Proc. Intl. Workshop Syst.-Level Intercon. Predict. (SLIP 2004), Paris, France, pp. 7–13 (February 2004)Google Scholar
  20. 20.
    Intel, Intel demonstrates industry’s first 32nm chip and next-generation Nehalem microprocessor architecture, September 18 (2007), http://www.intel.com/pressroom/archive/releases/2007/20070918corp_a.htm
  21. 21.
    Meindl, J.D.: Beyond Moore’s law: The interconnect era. Comp. in Sci. & Eng. 5, 20–24 (2003)CrossRefGoogle Scholar
  22. 22.
    Dally, W.J.: The end of denial architecture and the rise of throughput computing. In: Intl. Symp. Asynch. Circ & Syst. (ASYNC 2009), Chapel Hill, NC, USA, May 17-20 (2009), http://asyncsymposium.org/async2009/slides/dally-async2009.pdf, Also presented at HiPC 2009 and DAC 2009, http://videos.dac.com/46th/wedkey/dally.html
  23. 23.
    Kuo, W.: Challenges related to reliability in nano electronics. IEEE Trans. Reliab. 55, 569–570 (2006)CrossRefGoogle Scholar
  24. 24.
    Beiu, V., Ibrahim, W.: On computing nano-architectures using unreliable nano-devices. In: Lyshevski, S.E. (ed.) Handbook of Nano and Molecular Electronics, ch. 12, pp. 12.1–49. Taylor & Francis, London (2007)Google Scholar
  25. 25.
    Heins, M.: In the eye of the DFM/DFY storm. EE Times, May 25 (2007), http://www.eetimes.com/showArticle.jhtml?articleID=199702741
  26. 26.
    McKee, S.A. (ed.): Special Issue on Reliable Computing. ACM J. Emerg. Tech. Comp. Syst. 3 (July 2007)Google Scholar
  27. 27.
    Jeng, S.-L., Lu, J.-C., Wang, K.: A review of reliability research on nanotechnology. IEEE Trans. Reliab. 56, 401–410 (2007)CrossRefGoogle Scholar
  28. 28.
    Lau, C., Orailoglu, A., Roy, K. (eds.): Special Issue on Nano-electronic Circuits and Nano-architectures. IEEE Trans. Circ. & Syst. I 54 (November 2007)Google Scholar
  29. 29.
    Beiu, V., Ibrahim, W., Makki, R.Z.: On wires driven by a few electrons. In: Proc. Intl. Northeast Workshop Circ. & Syst. (NEWCAS 2009), Toulouse, France, June 28-July 1, pp. 1–4 (2009); art. 5290448Google Scholar
  30. 30.
    Beiu, V., Ibrahim, W.: On CMOS circuit reliability from the MOSFETs and the input vectors. In: Proc. Intl. Conf. Dependable Syst. & Nets. (DSN 2009), Estoril, Lisbon, Portugal, June 29-July 2 (2009) (in press), http://spiderman-2.laas.fr/WDSN09/WDSN09_files/Texts/WDSN09-2-2-Beiu.pdf
  31. 31.
    Landman, B.S., Russo, R.L.: On a pin versus block relationship for partitions of logic graphs. IEEE Trans. Comp. C-20, 1469–1479 (1971)CrossRefGoogle Scholar
  32. 32.
    Rent, E.F.: Microminiature packaging—Logic block to pin ratio. IBM Memoranda, November 28-December 12 (1960) (see also [34])Google Scholar
  33. 33.
    Lanzerotti, M.Y., Fiorenza, G., Rand, R.A.: Interpretation of Rent’s rule for ultralarge-scale integrated circuit designs, with an application to wirelength distribution models. IEEE Trans. VLSI Syst. 12, 1330–1347 (2004)CrossRefGoogle Scholar
  34. 34.
    Lanzerotti, M.Y., Fiorenza, G., Rand, R.A.: Microminiature packaging and integrated circuitry: The work of E. F. Rent, with an application to on-chip interconnection. IBM J. R&D 49, 777–803 (2005), CrossRefGoogle Scholar
  35. 35.
    Donath, W.E.: Placement and average interconnection lengths of computer logic. IEEE Trans. Circ. & Syst. 26, 272–277 (1979)CrossRefzbMATHGoogle Scholar
  36. 36.
    Bakoglu, H.B.: Circuits, Interconnections, and Packaging for VLSI. Addison-Wesley, Reading (1990)Google Scholar
  37. 37.
    Davis, J.A., De, V.H., Meindl, J.D.: A stochastic wire-length distribution for gigascale integration (GSI)—Part I: Derivation and validation. IEEE Trans. Electr. Dev. 45, 580–589 (1998)CrossRefGoogle Scholar
  38. 38.
    Davis, J.A., De, V.H., Meindl, J.D.: A stochastic wire-length distribution for gigascale integration (GSI)—Part II: Applications to clock frequency, power dissipation, and chip size estimation. IEEE Trans. Electr. Dev. 45, 590–597 (1998)CrossRefGoogle Scholar
  39. 39.
    Christie, P., Stroobandt, D.: The interpretation and application of Rent’s rule. IEEE Trans. VLSI Syst. 8, 639–648 (2000)CrossRefGoogle Scholar
  40. 40.
    Dambre, J., Stroobandt, D., Campenhout, J.V.: Toward the accurate prediction of placement wire length distributions in VLSI circuits. IEEE Trans. VLSI Syst. 12, 339–348 (2004)CrossRefGoogle Scholar
  41. 41.
    Das, S., Chandrakasan, A.P., Reif, R.: Calibration of Rent’s rule models for three-dimensional integrated circuits. IEEE Trans. VLSI Syst. 12, 359–366 (2004)CrossRefGoogle Scholar
  42. 42.
    Lanzerotti, M.Y., Fiorenza, G., Rand, R.A.: Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry. In: Proc. Intl. Workshop Syst. Level Interconn. Predict. (SLIP 2005), San Francisco, CA, USA, pp. 43–50 (April 2005)Google Scholar
  43. 43.
    Otten, R.H.J.M., Stravers, P.: Challenges in physical chip design. In: Proc. Intl. Conf. Comp. Aided Design (ICCAD 2000), San Jose, CA, USA, pp. 84–91 (November 2000)Google Scholar
  44. 44.
    DeHon, A.: Rent’s rule based switching requirements. In: Proc. Syst.-Level Intercon. Predict. Workshop (SLIP 2001), Sonoma, CA, USA, pp. 197–204 (March 2001)Google Scholar
  45. 45.
    DeHon, A.: Unifying mesh- and tree-based programmable interconnect. IEEE Trans. VLSI Syst. 12, 1051–1065 (2004)CrossRefGoogle Scholar
  46. 46.
    Kumar, A., Tiwari, S.: Testing and defect tolerance: A Rent’s rule based analysis and implications on nanoelectronics. In: Proc. Intl. Symp. Defect & Fault Tolerance VLSI Syst. (DFT 2004), Ithaca, NY, USA, pp. 280–288 (October 2004)Google Scholar
  47. 47.
    Tiwari, S., Kumar, A., Liu, C.C., Lin, H., Kim, S.K., Silva, H.: Electronics at nanoscale: Fundamental and practical challenges, and emerging directions. In: Proc. Conf. Emerg. Tech. – Nanoelectr. (NanoSingapore 2006), Singapore, pp. 481–486 (January 2006)Google Scholar
  48. 48.
    Lanzerotti, M.Y., Fiorenza, G., Rand, R.A.: Impact of interconnect length changes on effective materials properties (dielectric constant). In: Austin, T.X. (ed.) Proc. Intl. Workshop Syst. Level Interconn. Predict. (SLIP 2007), Austin, TX, USA, pp. 73–80 (March 2007)Google Scholar
  49. 49.
    Zarkesh-Ha, P., Davis, J.A., Loh, W., Meindl, J.D.: On a pin versus gate relationship for heterogeneous systems: Heterogeneous Rent’s rule. In: Proc. Intl. Custom Integr. Circ. Conf. (CICC 1998), Santa Clara, CA, USA, May 11-14, pp. 93–96 (1998)Google Scholar
  50. 50.
    Joyner, J.W., Zarkesh-Ha, P., Meindl, J.D.: Global interconnect design in a three-dimensional system-on-a-chip. IEEE Trans. VLSI Syst. 4, 367–372 (2004)CrossRefGoogle Scholar
  51. 51.
    Dally, W.J., Towels, B.: Principles and Practices of Interconnection Networks. Elsevier/ Morgan Kaufmann, San Mateo, CA, USA (2004)Google Scholar
  52. 52.
    Preparata, F.P., Vuillemin, J.: The cube-connected cycles: A versatile network for parallel computation. Comm. ACM 24, 300–309 (1981)MathSciNetCrossRefGoogle Scholar
  53. 53.
    Wittie, L.D.: Communication structures for large networks of microcomputers. IEEE Trans. Comp. 30, 264–273 (1981)CrossRefGoogle Scholar
  54. 54.
    Leiserson, C.E.: Fat-trees: Universal networks for hardware-efficient supercomputing. IEEE Trans. Comp. 34, 892–901 (1985)CrossRefGoogle Scholar
  55. 55.
    Szymanski, T.: Hypermeshes optical interconnection networks for parallel computing. J. Par. & Distrib. Comp. 26, 1–23 (1995)CrossRefzbMATHGoogle Scholar
  56. 56.
    Bhuyan, L.N., Agrawal, D.P.: Generalized hypercube and hyperbus structures for a computer network. IEEE Trans. Comp. 33, 323–333 (1984)CrossRefzbMATHGoogle Scholar
  57. 57.
    Ghose, K., Desai, K.R.: Hierarchical cubic networks. IEEE Trans. Comp. 6, 427–435 (1995)Google Scholar
  58. 58.
    Ganesan, E., Pradhan, D.K.: The hyper-deBruijn networks: Scalable versatile architecture. IEEE Trans. Par. & Distrib. Syst. 4, 962–978 (1993)CrossRefGoogle Scholar
  59. 59.
    Saad, Y., Schultz, M.H.: Topological properties of hypercubes. IEEE Trans. Comp. 37, 867–872 (1988)CrossRefGoogle Scholar
  60. 60.
    Louri, A., Sung, H.: A scalable optical hypercube-based interconnection network for massively parallel computing. Appl. Optics 33, 7588–7598 (1994)CrossRefGoogle Scholar
  61. 61.
    Ohring, S., Das, S.K.: Folded Petersen cube networks: New competitors for the hypercubes. IEEE Trans. Par. & Distrib. Syst. 7, 151–168 (1996)CrossRefGoogle Scholar
  62. 62.
    Balkan, A.O., Qu, G., Vishkin, U.: Mesh-of-trees and alternative interconnection networks for single-chip parallelism. IEEE Trans. VLSI Syst. 17, 1419–1432 (2009)CrossRefGoogle Scholar
  63. 63.
    Laughlin, S.B., Sejnowski, T.J.: Communication in neural networks. Science 301, 1870–1874 (2003)CrossRefGoogle Scholar
  64. 64.
    Zhang, K., Sejnowski, T.J.: A universal scaling law between gray matter and white matter of cerebral cortex. Proc. Natl. Acad. Sci. USA 97, 5621–5626 (2000)CrossRefGoogle Scholar
  65. 65.
    Beiu, V., Amer, H., McGinnity, M.: On global communications for nano-architectures – Brain versus Rent’s rule. In: Proc. Conf. Design Circ. & ICs (DCIS 2007), Seville, Spain, pp. 305–310 (November 2007)Google Scholar
  66. 66.
    Hammerstrom, D.: Biologically inspired nanoarchitectures. In: Computer-Aided Network Design Workshop (CAND 2007), Long Beach, CA, USA (September 2007)Google Scholar
  67. 67.
    Le Bihan, D.: The ‘wet mind’: Water and functional neuroimaging (introductory review). Phys. Med. and Biol. 52(7), R57–R90 (2007)MathSciNetCrossRefGoogle Scholar
  68. 68.
    Jirsa, V.K., McIntosh, A.R. (eds.): Handbook of Brain Connectivity. Springer: Complexity (Understanding Complex Systems), Berlin (2007)Google Scholar
  69. 69.
    Le Bihan, D., Urayama, S., Aso, T., Hanakawa, T., Fukuyama, H.: Direct and fast detection of neuronal activation in the human brain with diffusion MRI. Proc. Natl. Acad. Sci. USA 103, 8263–8268 (2006)CrossRefGoogle Scholar
  70. 70.
    Achard, S., Salvador, R., Whitcher, B., Suckling, J., Bullmore, E.: A resilient, low-frequency, small-world human brain functional network with highly connected association cortical hubs. J. Neurosci. 26, 63–72 (2006)CrossRefGoogle Scholar
  71. 71.
    Achard, S., Bullmore, E.: Efficiency and cost of economical brain functional networks. PLoS Comput. Biol. 3, 174–183 (2007)CrossRefGoogle Scholar
  72. 72.
    Merboldt, K.D., Hanckie, W., Frahm, J.: Self-diffusion NMR imaging using stimulated echoes. J. Magnetic Resonance 64, 479–486 (1985)Google Scholar
  73. 73.
    O’Donnell, L., Haker, S., Westin, C.-F.: New approaches to estimation of white matter connectivity in diffusion tensor MRI: Elliptic PDEs and geodesics in a tensor-warped space. In: Dohi, T., Kikinis, R. (eds.) MICCAI 2002. LNCS, vol. 2488, pp. 459–466. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  74. 74.
    Sebastiani, G., Pasquale, F., Barone, P.: Quantifying human brain connectivity from diffusion tensor MRI. J. Math. Imag. & Vision 25, 227–244 (2006)MathSciNetCrossRefzbMATHGoogle Scholar
  75. 75.
    Prados, E., Soatto, S., Lenglet, C., Pons, J.-P., Wotawa, N., Deriche, R., Faugeras, O.: Control theory and fast marching techniques for brain connectivity mapping. In: Proc. Intl. Conf. Comp. Vis. & Pattern Recog. (CVPR 2006), New York, NY, USA, vol. 1, pp. 1076–1083 (June 2006)Google Scholar
  76. 76.
    The Blue Brain Project, http://bluebrain.epfl.ch/
  77. 77.
    Bialek, W., Rieke, F.: Reliability and information transmission in spiking neurons. Trends Neurosci. 15, 428–434 (1992)CrossRefGoogle Scholar
  78. 78.
    Stevens, C.F.: Neuronal communication. Cooperativity of unreliable neurons. Current Biol. 4, 268–269 (1994)CrossRefGoogle Scholar
  79. 79.
    Smetters, D.K., Zador, A.: Synaptic transmission: Noisy synapses and noisy neurons. Current Biol. 6, 1217–1218 (1996)CrossRefGoogle Scholar
  80. 80.
    Lisman, J.E.: Bursts as a unit of neural information: Making unreliable synapses reliable. Trends Neurosci. 20, 38–43 (1997)CrossRefGoogle Scholar
  81. 81.
    Zador, A.: Impact of synaptic unreliability on the information transmitted by spiking neurons. J. Neurophysiol. 79, 1219–1229 (1998)Google Scholar
  82. 82.
    Manwani, A., Koh, C.: Detecting and estimating signals over noisy and unreliable synapses: Information-theoretic analysis. Neural Comp. 13, 1–33 (2001)CrossRefzbMATHGoogle Scholar
  83. 83.
    Levy, W.B., Baxter, R.A.: Energy-efficient neuronal computation via quantal synaptic failures. J. Neurosci. 22, 4746–4755 (2002)Google Scholar
  84. 84.
    Chklovskii, D.B.: Exact solution for the optimal neuronal layout problem. Neural Comp. 16, 2067–2078 (2004)CrossRefzbMATHGoogle Scholar
  85. 85.
    Madappuram, B.A.M., Beiu, V., Kelly, P.M., McDaid, L.J.: On Brain-inspired Connectivity and Hybrid Network Topologies. In: Proc. Intl. Symp. Nanoscale Archs. (NanoArch 2008), Anaheim, CA, USA, pp. 54–61 (June 2008)Google Scholar
  86. 86.
    Beiu, V., Madappuram, B.A.M., McGinnity, M.: On Brain-inspired Hybrid Topologies for Nano-architectures — A Rent’s Rule Approach. In: Proc. Intl. Conf. Embedded Comp. Syst. (IC-SAMOS 2008), Samos, Greece, pp. 33–40 (July 2008)Google Scholar
  87. 87.
    Teuscher, C., Gulbahce, N., Rohlf, T.: Assessing random dynamical network architectures for nanoelectronics. In: Proc. Intl. Symp. Nanoscale Archs. (NanoArch 2008), Anaheim, CA, USA, pp. 16–23 (June 2008)Google Scholar
  88. 88.
    Karbowski, J.: Optimal wiring principle and plateaus in the degree of separation for cortical neurons. Phys. Rev. Lett. 86, 3674–3677 (2001)CrossRefGoogle Scholar
  89. 89.
    Johansson, C.: Towards cortex isomorphic attractor neural networks. Lic. Thesis, School Comp. Sci. & Comm., Royal Inst. Tech. (KTH), Stockholm, Sweden (June 2004), http://www.nada.kth.se/~cjo/publications/lic.pdf
  90. 90.
    Silver, R., Boahen, K., Grillner, S., Kopell, N., Olsen, K.L.: Neurotech for neuroscience: Unifying concepts, organizing principles, and emerging tools. J. Neurosci. 27, 11807–11819 (2007)CrossRefGoogle Scholar
  91. 91.
    Djurfeldt, M., Lundqvist, M., Johansson, C., Rehn, M., Ekeberg, Ö., Lansner, A.: Brain-scale simulation of the neocortex on the IBM Blue Gene/L supercomputer. IBM J. R& D (Sp. Issue Appls. of Massively Par. Syst.) 52, 31–41 (2008)Google Scholar
  92. 92.
    Reda, S.: Using circuit structural analysis techniques for network in system biology. In: Proc. Intl. Workshop Syst.-Level Intercon. Predict. (SLIP 2009), San Francisco, CA, USA, July 26-27, pp. 37–44 (2009)Google Scholar
  93. 93.
    von Neumann, J.: The Computer and the Brain. Yale Univ. Press, New Haven (1958)zbMATHGoogle Scholar
  94. 94.
    Hammerstrom, D.: The connectivity analysis of simple associations –or– How many connections do we need? In: Anderson, D.Z. (ed.) Neural Info. Proc. Syst. (NIPS 1987), pp. 338–347. Amer. Inst. of Physics (IoP), Denver (1988)Google Scholar
  95. 95.
    Vitányi, P.M.B.: Locality, communication, and interconnect length in multicomputers. SIAM J. Comput. 17, 659–672 (1988)MathSciNetCrossRefzbMATHGoogle Scholar
  96. 96.
    Fernández, A., Efe, K.: Bounds on the VLSI layout complexity of homogeneous product networks. In: Proc. Intl. Symp. Parallel Archs., Algs. & Networks (ISPAN 1994), Kanazawa, Japan, pp. 41–48 (December 1994)Google Scholar
  97. 97.
    Legenstein, R.A.: The wire-length complexity of neural networks. PhD dissertation, Inst. Theor. Comp. Sci., Graz Univ. Tech., Graz, Austria (November 2001), http://www.igi.tugraz.at/legi/psfiles/legi_diss.pdf
  98. 98.
    Kyogoku, T., Inoue, J., Nakashima, H., Uezono, T., Okada, K., Masu, K.: Wire length distribution model considering core utilization for system on chip. In: Proc. Intl. Symp. VLSI (ISVLSI 2005), Tampa, FL, USA, pp. 276–277 (May 2005)Google Scholar
  99. 99.
    Ho, R.: On-chip wires: Scaling and efficiency. PhD dissertation, EE Dept., Stanford Univ., Stanford, CA, USA (August 2003), http://www-vlsi.stanford.edu/papers/rh_thesis.pdf
  100. 100.
    Ho, R.: Interconnection technologies. In: Workshop on On- and Off-Chip Interconn. Nets for Multicore Syst. (OCIN 2006), Stanford, CA, USA (December 2006), http://www.ece.ucdavis.edu/~ocin06/talks/ho.pdf
  101. 101.
    Burleson, W., Maheshwari, A.: VLSI Interconnects: A Design Perspective. Elsevier/Morgan Kaufman, San Francisco, CA, USA (in progress); Burleson, W.: Statistical design issues and tradeoffs in on-chip interconnects. In: Intl. Forum Appl.-specific Multi-Proc. SoC (MPSoC 2006), Estes Park, CO, USA (August 2006), http://www.mpsoc-forum.org/2006/slides/Burleson.pdf
  102. 102.
    Joachim, C., Ratner, M.A.: Molecular electronics: Some views on transport junctions and beyond. Proc. Natl. Acad. Sci. USA 102, 8801–8808 (2005)CrossRefGoogle Scholar
  103. 103.
    Heimburg, T., Jackson, A.D.: On soliton propagation in biomembranes and nerves. Proc. Natl. Acad. Sci. USA 102, 9790–9795 (2005)CrossRefGoogle Scholar
  104. 104.
    Ricketts, D.S., Li, X., Sun, N., Woo, K., Ham, D.: On the self-generation of electrical soliton pulses. IEEE J. Solid-State Circ. 42, 1657–1668 (2007)CrossRefGoogle Scholar
  105. 105.
    Tuffy, F., McDaid, L.J., Kwan, V.W., Alderman, J., McGinnity, T.M., Santos, J.A., Kelly, P.M., Sayers, H.: Inter-neuron communication strategies for spiking neural networks. Neurocomp. 71, 30–44 (2007)CrossRefGoogle Scholar
  106. 106.
    Beausoleil, R.G., Kuekes, P.J., Snider, G.S., Wang, S.-Y., Williams, R.S.: Nanoelectronic and nanophotonic interconnect. Proc. IEEE 96, 230–247 (2008)CrossRefGoogle Scholar
  107. 107.
    Johnson, R.C.: HP targets silicon phonics. EE Times, May 14 (2008), http://www.eetimes.com/showArticle.jhtml?articleID=207800143
  108. 108.
    Merritt, R.: Potholes seen on road to silicon photonics. EE Times, January 28 (2009), http://www.eetimes.com/showArticle.jhtml?articleID=212903357

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Valeriu Beiu
    • 1
    • 2
  • Basheer A. M. Madappuram
    • 1
    • 2
  • Peter M. Kelly
    • 2
  • Liam J. McDaid
    • 2
  1. 1.Faculty of Information Technology, Center for Neural Inspired Nano Architectures (CNINA)United Arab Emirates UniversityAl AinUAE
  2. 2.School of Intelligent SystemsUniversity of UlsterMageeUK

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