Exploiting Abstraction for Efficient Formal Verification of DSPs with Arrays of Reconfigurable Functional Units

  • Miroslav N. Velev
  • Ping Gao
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6991)

Abstract

We compare two approaches for efficient formal verification of the integration of pipelined processor cores with arrays of reconfigurable functional units. The processors are modeled at a high level of abstraction, using a subset of Verilog, in a way that allows us to exploit the property of Positive Equality that results in significant simplifications of the solution space, and orders of magnitude speedup relative to previous methods. The presented techniques allow us to formally verify the integration of pipelined processors, including complex Digital Signal Processors (DSPs), with arrays of reconfigurable functional units of any size, where the reconfigurable functional units have any design, and for any topology of the connections between them. Such architectures are becoming increasingly used because of their much higher performance and reduced power consumption relative to conventional processors. One of the compared two approaches, which abstracts the entire array of reconfigurable functional units, results in at least 3 orders of magnitude speedup relative to the other approach that models the exact number of reconfigurable functional units and abstracts the design of each and the network that connects them, such that the speedup is increasing with the size of the array. To the best of our knowledge, this is the first work on automatic formal verification of pipelined processors with arrays of reconfigurable functional units.

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References

  1. 1.
    Aagaard, M.D., Day, N.A., Lou, M.: Relating Multi-Step and Single-Step Microprocessor Correctness Statements. In: Aagaard, M.D., O’Leary, J.W. (eds.) FMCAD 2002. LNCS, vol. 2517, pp. 123–141. Springer, Heidelberg (2002)CrossRefGoogle Scholar
  2. 2.
    Aagaard, M.D., Cook, B., Day, N.A., Jones, R.B.: A Framework for Superscalar Microprocessor Correctness Statements. Software Tools for Technology Transfer (STTT) 4(3), 298–312 (2003)CrossRefMATHGoogle Scholar
  3. 3.
    Ackermann, W.: Solvable Cases of the Decision Problem. North-Holland, Amsterdam (1954)MATHGoogle Scholar
  4. 4.
    Anglia, STMicroelectronics Adds DSP to Reconfigurable-Processor SoC for Wireless Infrastructure Applications (March 2006), http://www.anglia.com/newsarchive/904.asp?article_id=1750
  5. 5.
    Asia and South Pacific Design Automation Conference (ASP-DAC 2009), Panel Discussion: Near-Future SoC Architectures—Can Dynamically Reconfigurable Processors be a Key Technology? (January 2009)Google Scholar
  6. 6.
    Blaauw, D., Das, S.: CPU, Heal Thyself: A Fault-Monitoring Microprocessor Design Can Save Power or Allow Overclocking. IEEE Spectrum 46(8), 40–43 (2009), http://spectrum.ieee.org/semiconductors/processors/cpu-heal-thyself/0 CrossRefGoogle Scholar
  7. 7.
    Bryant, R.E., German, S., Velev, M.N.: Processor Verification Using Efficient Reductions of the Logic of Uninterpreted Functions to Propositional Logic. ACM Transactions on Computational Logic 2(1), 93–134 (2001)MathSciNetCrossRefGoogle Scholar
  8. 8.
    Bryant, R.E., Velev, M.N.: Boolean Satisfiability with Transitivity Constraints. ACM Transactions on Computational Logic (TOCL) 3(4), 604–627 (2002)MathSciNetCrossRefMATHGoogle Scholar
  9. 9.
    Burch, J.R., Dill, D.L.: Automated Verification of Pipelined Microprocessor Control. In: Dill, D.L. (ed.) CAV 1994. LNCS, vol. 818, pp. 68–80. Springer, Heidelberg (1994)CrossRefGoogle Scholar
  10. 10.
    Burch, J.R.: Techniques for Verifying Superscalar Microprocessors. In: Design Automation Conference (DAC 1996), pp. 552–557 (June 1996)Google Scholar
  11. 11.
    Das, S., Tokunaga, C., Pant, S., Ma, W.-H., Kalaiselvan, S., Lai, K., Bull, D.M., Blaauw, D.T.: RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance. IEEE Journal of Solid-State Circuits 44(1), 32–48 (2009)CrossRefGoogle Scholar
  12. 12.
    DPReview, Casio Introduces Exilim EX-ZR10 with Back-Illuminated Sensor (September 2010), http://www.dpreview.com/news/1009/10092015casioexzr10.asp
  13. 13.
    EDACafe, Panasonic Deploys Reconfigurable Logic in Professional AV Products (November 2007), www10.edacafe.com/nbc/articles/view_article.php?section=CorpNews&articleid=462449
  14. 14.
    Eén, N., Sörensson, N.: MiniSat: A SAT Solver with Conflict-Clause Minimization. In: Bacchus, F., Walsh, T. (eds.) SAT 2005. LNCS, vol. 3569, pp. 61–75. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  15. 15.
    Free Press Release, Sony Details PSP Chip Specs (PlayStation Portable Game Player) (June 2007), http://www.free-press-release.com/news/200706/1182092979.html
  16. 16.
    Goel, A., Sajid, K., Zhou, H., Aziz, A., Singhal, V.: BDD Based Procedures for a Theory of Equality with Uninterpreted Functions. Formal Methods in System Design 22(3), 205–224 (2003)CrossRefMATHGoogle Scholar
  17. 17.
    Goldberg, E., Novikov, Y.: BerkMin: A Fast and Robust Sat-Solver. In: Design, Automation and Test in Europe (DATE 2002), pp. 142–149 (March 2002)Google Scholar
  18. 18.
    Intel Corporation, IA-64 Application Developer’s Architecture Guide (May 1999), http://developer.intel.com/design/ia-64/architecture.htm
  19. 19.
    Kim, Y., Mahapatra, R.N.: Design of Low-Power Coarse-Grained Reconfigurable Architectures. CRC Press, Boca Raton (2011)Google Scholar
  20. 20.
    Lahiri, S., Pixley, C., Albin, K.: Experience with Term Level Modeling and Verification of the M∙CORE TM Microprocessor Core. In: International Workshop on High Level Design, Validation and Test (HLDVT 2001), pp. 109–114 (November 2001)Google Scholar
  21. 21.
    Le Berre, D., Simon, L.: Results from the SAT 2004 SAT Solver Competition. In: SAT 2004 (May 2004)Google Scholar
  22. 22.
    Mei, B., De Sutter, B., Vander Aa, T., Wouters, M., Dupont, S.: Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder. Journal of Signal Processing Systems 51, 225–243 (2008)CrossRefGoogle Scholar
  23. 23.
    Moskewicz, M.W., Madigan, C.F., Zhao, Y., Zhang, L., Malik, S.: Chaff: Engineering an Efficient SAT Solver. In: 38th Design Automation Conference (DAC 2001) (June 2001)Google Scholar
  24. 24.
    Pipatsrisawat, K., Darwiche, A.: A Lightweight Component Caching Scheme for Satisfiability Solvers. In: Marques-Silva, J., Sakallah, K.A. (eds.) SAT 2007. LNCS, vol. 4501, pp. 294–299. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  25. 25.
    Pnueli, A., Rodeh, Y., Strichman, O., Siegel, M.: The Small Model Property: How Small Can It Be? Journal of Information and Computation 178(1) (2002)Google Scholar
  26. 26.
    Ryan, L.: Siege SAT Solver, http://www.cs.sfu.ca/~loryan/personal
  27. 27.
    Sharangpani, H., Arora, K.: Itanium Processor Microarchitecture. IEEE Micro. 20(5), 24–43 (2000)CrossRefGoogle Scholar
  28. 28.
    Velev, M.N., Bryant, R.E.: Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking. In: Gopalakrishnan, G.C., Windley, P. (eds.) FMCAD 1998. LNCS, vol. 1522, pp. 18–35. Springer, Heidelberg (1998)CrossRefGoogle Scholar
  29. 29.
    Velev, M.N., Bryant, R.E.: Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors. In: 36th Design Automation Conference (DAC 1999), pp. 397–401 (June 1999)Google Scholar
  30. 30.
    Velev, M.N., Bryant, R.E.: Superscalar Processor Verification Using Efficient Reductions of the Logic of Equality with Uninterpreted Functions to Propositional Logic. In: Pierre, L., Kropf, T. (eds.) CHARME 1999. LNCS, vol. 1703, pp. 37–53. Springer, Heidelberg (1999)CrossRefGoogle Scholar
  31. 31.
    Velev, M.N., Bryant, R.E.: Formal Verification of Superscalar Microprocessors with Multicycle Functional Units, Exceptions, and Branch Prediction. In: DAC 2000, pp. 112–117 (June 2000)Google Scholar
  32. 32.
    Velev, M.N.: Formal Verification of VLIW Microprocessors with Speculative Execution. In: Emerson, E.A., Sistla, A.P. (eds.) CAV 2000. LNCS, vol. 1855, pp. 86–98. Springer, Heidelberg (2000)CrossRefGoogle Scholar
  33. 33.
    Velev, M.N.: Automatic Abstraction of Memories in the Formal Verification of Superscalar Microprocessors. In: Margaria, T., Yi, W. (eds.) TACAS 2001. LNCS, vol. 2031, pp. 252–267. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  34. 34.
    Velev, M.N.: Using Rewriting Rules and Positive Equality to Formally Verify Wide-Issue Out-Of-Order Microprocessors with a Reorder Buffer. In: Design, Automation and Test in Europe (DATE 2002), pp. 28–35 (March 2002)Google Scholar
  35. 35.
    Velev, M.N., Bryant, R.E.: Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors. Journal of Symbolic Computation (JSC) 35(2), 73–106 (2003)MathSciNetCrossRefMATHGoogle Scholar
  36. 36.
    Velev, M.N.: Automatic Abstraction of Equations in a Logic of Equality. In: Cialdea Mayer, M., Pirri, F. (eds.) TABLEAUX 2003. LNCS, vol. 2796, pp. 196–213. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  37. 37.
    Velev, M.N.: Using Automatic Case Splits and Efficient CNF Translation to Guide a SAT-Solver When Formally Verifying Out-of-Order Processors. In: Artificial Intelligence and Mathematics (AI&MATH 2004), pp. 242–254 (January 2004)Google Scholar
  38. 38.
    Velev, M.N.: Efficient Translation of Boolean Formulas to CNF in Formal Verification of Microprocessors. In: Asia & South Pacific Design Autom. Conf., pp. 310–315 (January 2004)Google Scholar
  39. 39.
    Velev, M.N.: Using Positive Equality to Prove Liveness for Pipelined Microprocessors. In: Asia and South Pacific Design Automation Conference, pp. 316–321 (January 2004)Google Scholar
  40. 40.
    Velev, M.N.: Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors. In: Design, Automation and Test in Europe (DATE 2004), pp. 266–271 (February 2004)Google Scholar
  41. 41.
    Velev, M.N.: Encoding Global Unobservability for Efficient Translation to SAT. In: International Conference on Theory and Applications of Satisfiability Testing (May 2004)Google Scholar
  42. 42.
    Velev, M.N.: Comparative Study of Strategies for Formal Verification of High-Level Processors. In: Int’l. Conf. on Computer Design (ICCD 2004), pp. 119–124 (October 2004)Google Scholar
  43. 43.
    Velev, M.N.: Comparison of Schemes for Encoding Unobservability in Translation to SAT. In: Asia & South Pacific Design Automation Conference (ASP-DAC 2005), pp. 1056–1059 (January 2005)Google Scholar
  44. 44.
    Velev, M.N., Bryant, R.E.: TLSim and EVC: A Term-Level Symbolic Simulator and an Efficient Decision Procedure for the Logic of Equality with Uninterpreted Functions and Memories. Int’l. Journal of Embedded Systems 1(1/2 ), 134–149 (2005)CrossRefGoogle Scholar
  45. 45.
    Velev, M.N.: Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle Functional Units. In: Borrione, D., Paul, W. (eds.) CHARME 2005. LNCS, vol. 3725, pp. 97–113. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  46. 46.
    Velev, M.N.: Using Abstraction for Efficient Formal Verification of Pipelined Processors with Value Prediction. In: International Symposium on Quality Electronic Design (2006)Google Scholar
  47. 47.
    Velev, M.N.: Formal Verification of Pipelined Microprocessors with Delayed Branches. In: ISQED 2006, pp. 296–299 (March 2006)Google Scholar
  48. 48.
    Velev, M.N., Gao, P.: Exploiting Hierarchical Encodings of Equality to Design Independent Strategies in Parallel SMT Decision Procedures for a Logic of Equality. In: High Level Design Validation and Test Workshop (HLDVT 2009), pp. 8–13 (November 2009)Google Scholar
  49. 49.
    Velev, M.N., Gao, P.: A Method for Debugging of Pipelined Processors in Formal Verification by Correspondence Checking. In: ASP-DAC 2010, pp. 619–624 (January 2010)Google Scholar
  50. 50.
    Velev, M.N., Gao, P.: Method for Formal Verification of Soft-Error Tolerance Mechanisms in Pipelined Microprocessors. In: Dong, J.S., Zhu, H. (eds.) ICFEM 2010. LNCS, vol. 6447, pp. 355–370. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  51. 51.
    Velev, M.N., Gao, P.: Automatic Formal Verification of Reconfigurable DSPs. In: Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 293–296 (January 2011)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Miroslav N. Velev
    • 1
  • Ping Gao
    • 1
  1. 1.Aries Design AutomationUSA

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