Model Checking and Co-simulation of a Dynamic Task Dispatcher Circuit Using CADP

  • Etienne Lantreibecq
  • Wendelin Serwe
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6959)

Abstract

The complexity of multiprocessor architectures for mobile multi-media applications renders their validation challenging. In addition, to provide the necessary flexibility, a part of the functionality is realized by software. Thus, a formal model has to take into account both hardware and software. In this paper we report on the use of LOTOS NT and CADP for the formal modeling and analysis of the DTD (Dynamic Task Dispatcher), a complex hardware block of an industrial hardware architecture developed by STMicroelectronics. Using LOTOS NT facilitated exploration of alternative design choices and increased the confidence in the DTD, by, on the one hand, automatic analysis of formal models easily understood by the architect of the DTD, and, on the other hand, co-simulation of the formal model with the implementation used for synthesis.

Keywords

Model Check Idle Mode Execution Scheme Host Processor Multiprocessor Architecture 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Etienne Lantreibecq
    • 1
  • Wendelin Serwe
    • 2
  1. 1.STMicroelectronicsGrenobleFrance
  2. 2.INRIA/LIGSt IsmierFrance

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