Symbolic Power Analysis of Cell Libraries

  • Matthias Raffelsieper
  • MohammadReza Mousavi
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6959)

Abstract

Cell libraries are collections of logic cores (cells) used to construct larger chip designs; hence, any reduction in their power consumption may have a major impact in the power consumption of larger designs. The power consumption of a cell is often determined by triggering it with all possible input values in all possible orders at each state. In this paper, we first present a technique to measure the power consumption of a cell more efficiently by reducing the number of input orders that have to be checked. This is based on symbolic techniques and analyzes the number of (weighted) wire chargings taking place. Additionally, we present a technique that computes for a cell all orders that lead to the same state, but differ in their power consumption. Such an analysis is used to select the orders that minimize the required power, without affecting functionality, by inserting sufficient delays. Both techniques have been evaluated on an industrial cell library and were able to efficiently reduce the number of orders needed for power characterization and to efficiently compute orders that consume less power for a given state and input-vector transition.

Keywords

Power Consumption Equivalence Class Input Vector Transition System Transition Relation 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Bogliolo, A., Benini, L., Ricco, B.: Power Estimation of Cell-Based CMOS Circuits. In: Proc. of DAC 1996, pp. 433–438. ACM, New York (1996)Google Scholar
  2. 2.
    Bryant, R.: Boolean Analysis of MOS Circuits. IEEE Transactions on Computer-Aided Design 6(4), 634–649 (1987)CrossRefGoogle Scholar
  3. 3.
    Huang, M., Kwok, R., Chan, S.-P.: An Empirical Algorithm for Power Analysis in Deep Submicron Electronic Designs. VLSI Design 14(2), 219–227 (2000)CrossRefGoogle Scholar
  4. 4.
    Nangate Inc. Open Cell Library v2008_10 SP1 (2008), http://www.nangate.com/openlibrary/.
  5. 5.
    Raffelsieper, M., Mousavi, M.R., Roorda, J.-W., Strolenberg, C., Zantema, H.: Formal Analysis of Non-determinism in Verilog Cell Library Simulation Models. In: Alpuente, M., Cook, B., Joubert, C. (eds.) FMICS 2009. LNCS, vol. 5825, pp. 133–148. Springer, Heidelberg (2009)CrossRefGoogle Scholar
  6. 6.
    Raffelsieper, M., Mousavi, M.R., Zantema, H.: Order-Independence of Vector-Based Transition Systems. In: Proc. of ACSD 2010, pp. 115–123. IEEE, Los Alamitos (2010)Google Scholar
  7. 7.
    Raghunathan, A., Dey, S., Jha, N.K.: Glitch Analysis and Reduction in Register Transfer Level Power Optimization. In: Proc. of DAC 1996, pp. 331–336. ACM, New York (1996)Google Scholar
  8. 8.
    Shen, W.-Z., Lin, J.-Y., Lu, J.-M.: CB-Power: A Hierarchical Cell-Based Power Characterization and Estimation Environment for Static CMOS Circuits. In: Proc. of ASP-DAC 1997, pp. 189–194. IEEE, Los Alamitos (1997)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Matthias Raffelsieper
    • 1
  • MohammadReza Mousavi
    • 1
  1. 1.Department of Computer ScienceTU/EindhovenEindhovenThe Netherlands

Personalised recommendations