A Design-for-Verification Framework for a Configurable Performance-Critical Communication Interface

Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6919)


In this paper we present a Design-for-Verification framework for a Configurable Performance-Critical Communication Interface. To manage the inherent complexity of the problem we decomposed the interface into independent parametrisable communication blocks. Tock-CSP was then used to model the timing and functional specifications of our interface. The FDR model checker and its tau-priority model were used to prove that the properties of the configured interface are within the properties of targeted communication protocols.


CSP tock-CSP Design-for-Verification tau-priority 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    AbuKharmeh, S., Eder, K., May, D.: Formal analysis of a programmable performance-critical processor communication interface. In: Proceedings of the 10th International Workshop on Automated Verification of Critical Systems (2010),
  2. 2.
    Altera Corporate: Stratix GX FPGA, Family Datasheet (2004)Google Scholar
  3. 3.
    American National Standards Institute: Standards for Local Area Networks: Carrier Sense Multiple Access with Collision Detection (CSMA-CD) - Standards 802.3. John Wiley & Sons, Inc., New York (1985)Google Scholar
  4. 4.
    ARM Ltd.: AMBATMSpecification Revision 2 (1999)Google Scholar
  5. 5.
    Böhm, P., Melham, T.: A refinement approach to design and verification of on-chip communication protocols. In: Proceedings of the 2008 International Conference on Formal Methods in Computer-Aided Design (2008)Google Scholar
  6. 6.
    Electronics Industries Association: EIA standard RS-232-C interface between data terminal equipment and data communication equipment employing serial data interchange. Tech. rep., Electronics Industries Association (1969)Google Scholar
  7. 7.
    Formal Systems: Failures-Divergence Refinement FDR2, User Manual, 2.91 edn. (May 2010)Google Scholar
  8. 8.
    Freescale Semiconductor Inc: MPC5121e serial peripheral interface (SPI). online (2009)Google Scholar
  9. 9.
    Hoare, C.A.R.: Communicating Sequential Processes. Prentice Hall International, Englewood Cliffs (2004)zbMATHGoogle Scholar
  10. 10.
    Horta, E.L., Lockwood, J.W., Taylor, D.E., Parlour, D.: Dynamic hardware plugins in an FPGA with partial run-time reconfiguration. In: Proceedings of the 39th Annual Design Automation Conference, DAC 2002, vol. (39), pp. 343–348. ACM, New York (2002)Google Scholar
  11. 11.
    International Organization for Standardization: ISO 11898-1:2003 - Road vehicles – Controller area network (CAN) – Part 1: Data link layer and physical signalling. Tech. rep., ISO (2003)Google Scholar
  12. 12.
    Kaizhi, Y.: Validating system requirements by functional decomposition and dynamic analysis. In: Proceedings of the 11th International Conference on Software Engineering, ICSE 1989, pp. 188–196. ACM, New York (1989)Google Scholar
  13. 13.
    Kuon, I., Rose, J.: Measuring the gap between FPGAs and ASICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 12(8), 203–215 (2007)CrossRefGoogle Scholar
  14. 14.
    May, D., Muller, H., Hedinger, P., Dixon, A., Owen, R., Richards, N.: XS1 Ports: use and specification. XMOS Ltd., 1.02 edn. (November 2008)Google Scholar
  15. 15.
    Microchip Inc: PIC16F87X Microcontrollers Datasheet (2001)Google Scholar
  16. 16.
    Müffke, F.: A better way to design communication protocols. Ph.D. thesis, University of Bristol (May 2004)Google Scholar
  17. 17.
    Open Microprocessor Systems Initiative: OMI 324: PI-Bus. Tech. rep., OMI (1994)Google Scholar
  18. 18.
    Ouaknine, J.: Discrete analysis of continuous behaviour in real-time concurrent systems. Ph.D. thesis, Oxford University (2001)Google Scholar
  19. 19.
    Philips Semiconductors: The I2C-Bus specification. Tech. rep., Philips (2000)Google Scholar
  20. 20.
    Roscoe, A.W.: Understanding Concurrent Systems, 1st edn. Texts in Computer Science. Springer, Heidelberg (2010)CrossRefzbMATHGoogle Scholar
  21. 21.
    Schneider, S.: Concurrent and Real Time Systems: The CSP Approach. John Wiley & Sons, Inc., New York (1999)Google Scholar
  22. 22.
    Seidel, K.: Case study: Specification and refinement of the PI-Bus. In: Naftalin, M., Bertrán, M., Denvir, T. (eds.) FME 1994. LNCS, vol. 873, pp. 532–546. Springer, Heidelberg (1994)CrossRefGoogle Scholar
  23. 23.
    Spars, J., Furber, S.: Principles of Asynchronous Circuit Design: A Systems Perspective. Kluwer Academic Publishers, Boston (2001)CrossRefGoogle Scholar
  24. 24.
    Tretmans, J.: A Formal Approach to Conformance Testing. Ph.D. thesis, University of Twente, Enschede (1992)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  1. 1.Computer Science DepartmentUniversity of BristolUnited Kingdom

Personalised recommendations