Improving the Robustness of Self-timed SRAM to Variable Vdds
The most efficient power saving method in digital systems is to scale Vdd, owing to the quadratic dependence of dynamic power consumption. This requires memory working under a wide range of Vdds in terms of performance and power saving requirements. A self-timed 6T SRAM was previously proposed, which adapts to the variable Vdd automatically. However due to leakage, the size of memory is restricted by process variations. This paper reports a new self-timed 10T SRAM cell with bit line keepers developed to improve robustness in order to work in a wide range of Vdds down to 0.3V under PVT variations. In addition, this paper briefly discusses the potential benefits of the self-timed SRAM for designing highly reliable systems and detecting the data retention voltage (DRV).
KeywordsSelf-Timed SRAM Robustness Energy Harvesting Low Power Systems DRV Handshake protocols Open Loop Control Closed Loop Control Reliable System Fault model Fault Detection PVT variations
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