Performance-Driven Clustering of Asynchronous Circuits

  • Georgios D. Dimou
  • Peter A. Beerel
  • Andrew M. Lines
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6951)

Abstract

This paper describes a novel approach for generating asynchronous circuits from HDL specifications by clustering the synthesized gates into asynchronous pipeline stages while preserving liveness, meeting throughput constraints, and minimizing area. The method enables a form of automatic re-pipelining in which the throughput of the resulting design is not limited to the clock frequency or the level of pipelining in the original RTL specification. The method is design-style agnostic and is thus applicable to many asynchronous design styles.

Keywords

Local Move Performance Target Pipeline Stage Asynchronous Circuit Token Buffer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Georgios D. Dimou
    • 1
  • Peter A. Beerel
    • 1
    • 2
  • Andrew M. Lines
    • 1
  1. 1.Fulcrum Microsystems Inc.CalabasasUSA
  2. 2.Ming Hsieh Dept. of Elec. Eng.University of Southern CaliforniaLos AngelesUSA

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