FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control

  • Mehrdad Majzoobi
  • Farinaz Koushanfar
  • Srinivas Devadas
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6917)

Abstract

The paper presents a novel and efficient method to generate true random numbers on FPGAs by inducing metastability in bi-stable circuit elements, e.g. flip-flops. Metastability is achieved by using precise programmable delay lines (PDL) that accurately equalize the signal arrival times to flip-flops. The PDLs are capable of adjusting signal propagation delays with resolutions higher than fractions of a pico second. In addition, a real time monitoring system is utilized to assure a high degree of randomness in the generated output bits, resilience against fluctuations in environmental conditions, as well as robustness against active adversarial attacks. The monitoring system employs a feedback loop that actively monitors the probability of output bits; as soon as any bias is observed in probabilities, it adjusts the delay through PDLs to return to the metastable operation region. Implementation on Xilinx Virtex 5 FPGAs and results of NIST randomness tests show the effectiveness of our approach.

Keywords

Clock Cycle Proportional Integral Derivative Proportional Integral Delay Difference SRAM Cell 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

References

  1. 1.
    Barak, B., Shaltiel, R., Tromer, E.: True random number generators secure in a changing environment. In: Walter, C.D., Koç, Ç.K., Paar, C. (eds.) CHES 2003. LNCS, vol. 2779, pp. 166–180. Springer, Heidelberg (2003)CrossRefGoogle Scholar
  2. 2.
    Bergeron, E., Feeley, M., Daigneault, M.A., David, J.: Using dynamic reconfiguration to implement high-resolution programmable delays on an FPGA. In: NEWCAS-TAISA, pp. 265–268 (2008)Google Scholar
  3. 3.
    Gassend, B., Clarke, D., van Dijk, M., Devadas, S.: Silicon physical random functions. In: CCS, pp. 148–160 (2002)Google Scholar
  4. 4.
    Jun, B., Kocher, P.: The Intel random number generator. In: Cryptography Research, Inc. (1999)Google Scholar
  5. 5.
    Lee, J., Lim, D., Gassend, B., Suh, G., van Dijk, M., Devadas, S.: A technique to build a secret key in integrated circuits for identification and authentication applications. In: Symposium on VLSI Circuits, pp. 176–179 (2004)Google Scholar
  6. 6.
    Majzoobi, M., Dyer, E., Elnably, A., Koushanfar, F.: Rapid FPGA characterization using clock synthesis and signal sparsity. In: International Test Conference, ITC (2010)Google Scholar
  7. 7.
    Majzoobi, M., Koushanfar, F.: FPGA time-bounded authentication. IEEE Transactions on Information Forensics and Security PP(99), 1 (2011)Google Scholar
  8. 8.
    Majzoobi, M., Koushanfar, F., Devadas, S.: FPGA PUF using programmable delay lines. In: IEEE Workshop on Information Forensics and Security (WIFS), pp. 1–6 (2010)Google Scholar
  9. 9.
    Majzoobi, M., Elnably, A., Koushanfar, F.: FPGA time-bounded unclonable authentication. In: Böhme, R., Fong, P.W.L., Safavi-Naini, R. (eds.) IH 2010. LNCS, vol. 6387, pp. 1–16. Springer, Heidelberg (2010)CrossRefGoogle Scholar
  10. 10.
    von Neumann, J.: Various techniques used in connection with random digits. von Neumann Collected Works 5, 768–770 (1963)Google Scholar
  11. 11.
    O’Donnell, C.W., Suh, G.E., Devadas, S.: PUF-based random number generation. In: MIT CSAIL CSG Technical Memo 481, p. 2004 (2004)Google Scholar
  12. 12.
    Schellekens, D., Preneel, B., Verbauwhede, I.: FPGA vendor agnostic true random number generator. In: Field Programmable Logic and Applications (FPL), pp. 1–6 (2006)Google Scholar
  13. 13.
    Suh, G., Devadas, S.: Physical unclonable functions for device authentication and secret key generation. In: Design Automation Conference (DAC), p. 914 (2007)Google Scholar
  14. 14.
    Sunar, B.: True Random Number Generators for Cryptography. In: Cryptographic Engineering. Springer, Heidelberg (2009)Google Scholar
  15. 15.
    Sunar, B., Martin, W.J., Stinson, D.R.: A provably secure true random number generator with built-in tolerance to active attacks. IEEE Transactions on Computers 58, 109–119 (2007)MathSciNetCrossRefGoogle Scholar
  16. 16.
    Wong, J.S.J., Sedcole, P., Cheung, P.Y.K.: Self-Measurement of Combinatorial Circuit Delays in FPGAs. ACM Transactions on Reconfigurable Technology and Systems 2(2), 1–22 (2009)CrossRefGoogle Scholar

Copyright information

© International Association for Cryptologic Research 2011

Authors and Affiliations

  • Mehrdad Majzoobi
    • 1
  • Farinaz Koushanfar
    • 1
  • Srinivas Devadas
    • 2
  1. 1.ECERice UniversityHouston
  2. 2.CSAILMassachusetts Institute of TechnologyCambridge

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