Correlation Bounds for Poly-size \(\mbox{\rm AC}^0\) Circuits with n1 − o(1) Symmetric Gates

  • Shachar Lovett
  • Srikanth Srinivasan
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6845)

Abstract

Average-case circuit lower bounds are one of the hardest problems tackled by computational complexity, and are essentially only known for bounded-depth circits with AND,OR,NOT gates (i.e. \(\mbox{\rm AC}^0\)). Faced with this adversity, one line of research has been to gradually augment \(\mbox{\rm AC}^0\) circuits with a small number of more general gates. Most results to date give lower bounds for quasi-polynomial size \(\mbox{\rm AC}^0\) circuits augmented by a poly-logarithmic number of gates, and the correlation bounds obtained are inverse quasi-polynomial.

We continue this line of research, but restrict our attention to polynomial size \(\mbox{\rm AC}^0\) circuits. Surprisingly, we show that this restriction allows us to prove much stronger results: we can augment the \(\mbox{\rm AC}^0\) circuit with n1 − o(1) many gates, and still obtain inverse exponential correlation bounds. Explicitly,

  1. 1

    Poly-size \(\mbox{\rm AC}^0\) circuits with n1 − o(1) arbitrary symmetric gates have exponentially small correlation with an explicitly given function.

     
  2. 2

    Poly-size \(\mbox{\rm AC}^0\) circuits with n1/2 − o(1) threshold gates have exponentially small correlation with the same explicit function.

     
  3. 3

    Poly-size \(\mbox{\rm AC}^0\) circuits with n1 − o(1) counting gates modulo s have exponentially small correlation with the sum of the bits modulo q, where s,q are co-prime.

     

Our proof techniques combine the meet-in-the-middle approach for circuit lower bounds with restrictions (due to Ajtai) that are tailored to polynomial-size circuits.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Shachar Lovett
    • 1
  • Srikanth Srinivasan
    • 1
  1. 1.Institute of Advanced StudyPrincetonUSA

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