Design Methodology of Dynamically Reconfigurable Network-on-Chip

  • Haiyun Gu
Conference paper

DOI: 10.1007/978-3-642-21762-3_14

Part of the Lecture Notes in Electrical Engineering book series (LNEE, volume 100)
Cite this paper as:
Gu H. (2011) Design Methodology of Dynamically Reconfigurable Network-on-Chip. In: Ma M. (eds) Communication Systems and Information Technology. Lecture Notes in Electrical Engineering, vol 100. Springer, Berlin, Heidelberg

Abstract

NoC (Network-on-Chip) is inherently suitable to the dynamic partial reconfiguration. DRNoC, combining these two promising technologies, will be a desirable platform for the next generation portable eletronic consuming products. Taking the irregular 2D mesh NoC as a study case, this paper discusses the design methodology of DRNoC, including the topology, router, mapping algorithm, routing algorithm, implementation and simulation of DRNoC.

Keywords

NoC dynamica reconfiguration Xilinx FPGA 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Haiyun Gu
    • 1
  1. 1.College of Information EngineeringShanghai Maritime UniversityChina

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