Revisiting Synthesis of GR(1) Specifications

  • Uri Klein
  • Amir Pnueli
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6504)

Abstract

The last few years have seen a rising interest in the problem of synthesizing systems from temporal logic specifications. One major contributor to this is the recent work of Piterman et al., which showed how polynomial time synthesis could be achieved for a class of LTL specifications that is large enough and expressive enough to cover an extensive number of complex, real-world, applications (despite a known doubly-exponential time lower bound for general LTL formulae). That approach has already been used extensively for the synthesis of various applications and as basis for further theoretical work on synthesis.

Here, we expose a fundamental flaw in the initial processing of specifications in that paper and demonstrate how it may produce incorrect results, declaring that specifications could not be synthesized when, in fact, they could. We then identify a class of specifications for which this initial processing is sound and complete. Thus, giving an insight to the reason that this problem arises in the first place. We also show that it can be easily checked whether specifications belong to the sound and complete class by using the same synthesis techniques. Finally, we show in the cases that specifications do not fall into this category how to modify them so that their processing is, indeed, both sound and complete.

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References

  1. 1.
    Abadi, M., Lamport, L.: The existence of refinement mappings. TCS 82(2), 253–284 (1991)MathSciNetCrossRefMATHGoogle Scholar
  2. 2.
    Alur, R., La Torre, S.: Deterministic generators and games for LTL fragments. TOCL 5(1), 1–25 (2004)MathSciNetCrossRefMATHGoogle Scholar
  3. 3.
    Asarin, E., Maler, O., Pnueli, A., Sifakis, J.: Controller synthesis for timed automata. In: Proc. SSC, pp. 469–474. Elsevier, Amsterdam (1998)Google Scholar
  4. 4.
    Bloem, R., Greimel, K., Henzinger, T.A., Jobstmann, B.: Synthsizing Robust Systems. In: Proc. FMCAD, pp. 85–92 (2009)Google Scholar
  5. 5.
    Bloem, R., Galler, S., Jobstmann, B., Piterman, N., Pnueli, A., Weiglhofer, M.: Automatic hardware synthesis from specifications: A case study. In: Proc. DATE, pp. 1188–1193 (2007)Google Scholar
  6. 6.
    Bloem, R., Galler, S., Jobstmann, B., Piterman, N., Pnueli, A., Weiglhofer, M.: Specify, compile, run: Hardware from PSL. In: Proc. COCV, vol. 190(4), pp. 3–16 (2007)Google Scholar
  7. 7.
    Büchi, J.R., Landweber, L.H.: Solving sequential conditions by finite-state strategies. TAMS 138, 295–311 (1969)MathSciNetCrossRefMATHGoogle Scholar
  8. 8.
    Church, A.: Logic, arithmetic and automata. In: Proc. 1962 Int. Congr. Math, Upsala, pp. 23–25 (1963)Google Scholar
  9. 9.
    Clarke, E.M., Emerson, E.A.: Design and synthesis of synchronization skeletons using branching time temporal logic. In: Kozen, D. (ed.) Proc. IBM Workshop on Logics of Programs. LNCS, vol. 131, pp. 52–71. Springer, Heidelberg (1982)CrossRefGoogle Scholar
  10. 10.
    Clarke, E.M., Emerson, E.A., Sistla, A.P.: Automatic verification of finite state concurrent systems using temporal logic specifications. TOPLAS 8, 244–263 (1986)CrossRefMATHGoogle Scholar
  11. 11.
    Chatterjee, K., Henzinger, T.A., Jobstmann, B.: Environment Assumptions for Synthesis. In: Proc. Concur, pp. 141–161 (2008)Google Scholar
  12. 12.
    Conner, D.C., Kress-Gazit, H., Choset, H., Rizzi, A., Pappas, G.J.: Valet parking without a valet. In: Proc. IROS, pp. 572–577. IEEE, Los Alamitos (2007)Google Scholar
  13. 13.
    Emerson, E.A., Halpern, J.Y.: ‘Sometimes’ and ‘not never’ revisited: On branching time versus linear time. JACM 33, 151–178 (1986)CrossRefMATHGoogle Scholar
  14. 14.
    Emerson, E.A., Sistla, A.P.: Deciding full branching time logic. I&C 61, 175–201 (1984)MathSciNetMATHGoogle Scholar
  15. 15.
    Hafer, T., Thomas, W.: Computation tree logic CTL* and path quantifiers in the monadic theory of the binary tree. In: Ottmann, T. (ed.) ICALP 1987. LNCS, vol. 267, pp. 269–279. Springer, Heidelberg (1987)CrossRefGoogle Scholar
  16. 16.
    Kesten, Y., Piterman, N., Pnueli, A.: Bridging the gap between fair simulation and trace inclusion. I&C 200(1), 36–61 (2005)MathSciNetMATHGoogle Scholar
  17. 17.
    Kress-Gazit, H., Fainekos, G.E., Pappas, G.J.: From structured english to robot motion. In: Proc. IROS, pp. 2717–2722. IEEE, Los Alamitos (2007)Google Scholar
  18. 18.
    Kress-Gazit, H., Fainekos, G.E., Pappas, G.J.: Where’s waldo? sensor-based temporal logic motion planning. In: Proc. ICRA, pp. 3116–3121. IEEE, Los Alamitos (2007)Google Scholar
  19. 19.
    Kugler, H., Plock, C., Pnueli, A.: Controller synthesis from LSC requirements. In: Chechik, M., Wirsing, M. (eds.) FASE 2009. LNCS, vol. 5503, pp. 79–93. Springer, Heidelberg (2009)CrossRefGoogle Scholar
  20. 20.
    Kugler, H., Segall, I.: Compositional synthesis of reactive systems from live sequence chart specifications. In: Kowalewski, S., Philippou, A. (eds.) TACAS 2009. LNCS, vol. 5505, pp. 77–91. Springer, Heidelberg (2009)CrossRefGoogle Scholar
  21. 21.
    ARM Ltd. AMBA specification (rev. 2) (1999), www.arm.com
  22. 22.
    Manna, Z., Wolper, P.: Synthesis of communicating processes from temporal logic specifications. TOPLAS 6, 68–93 (1984)CrossRefMATHGoogle Scholar
  23. 23.
    Piterman, N., Pnueli, A., Sa’ar, Y.: Synthesis of reactive(1) designs. In: Emerson, E.A., Namjoshi, K.S. (eds.) VMCAI 2006. LNCS, vol. 3855, pp. 364–380. Springer, Heidelberg (2005)CrossRefGoogle Scholar
  24. 24.
    Pnueli, A.: Verification and synthesis of reactive programs. Marktoberdorf Summer School Lectures (August 2006)Google Scholar
  25. 25.
    Pnueli, A., Klein, U.: Synthesis of programs from temporal property specifications. In: Proc. MEMOCODE, pp. 1–7. IEEE Press, Los Alamitos (2009)Google Scholar
  26. 26.
    Pnueli, A., Rosner, R.: On the synthesis of a reactive module. In: Proc. POPL, pp. 179–190 (1989)Google Scholar
  27. 27.
    Pnueli, A., Zaks, A.: On the merits of temporal testers. In: Grumberg, O., Veith, H. (eds.) 25 Years of Model Checking. LNCS, vol. 5000, pp. 172–195. Springer, Heidelberg (2008)CrossRefGoogle Scholar
  28. 28.
    Rabin, M.O.: Automata on Infinite Objects and Church’s Problem. Amer. Math. Soc. Regional Conference Series in Mathematics, vol. 13 (1972)Google Scholar
  29. 29.
    Roveri, M., Bloem, R., Tschaltev, A., Jobstmann, B.: Personal Communication (2006)Google Scholar
  30. 30.
    Sohail, S., Somenzi, F.: Safety first: A two-stage algorithm for LTL games. In: Proc. FMCAD, pp. 77–84. IEEE Press, Los Alamitos (2009)Google Scholar
  31. 31.
    Sohail, S., Somenzi, F., Ravi, K.: A hybrid algorithm for LTL games. In: Logozzo, F., Peled, D.A., Zuck, L.D. (eds.) VMCAI 2008. LNCS, vol. 4905, pp. 309–323. Springer, Heidelberg (2008)CrossRefGoogle Scholar
  32. 32.
    Wilke, T.: Alternating tree automata, parity games, and modal μ-calculus. Bull. Soc. Math. Belg. 8(2) (2001)Google Scholar
  33. 33.
    Wongpiromsarn, T., Topcu, U., Murray, R.M.: Receding horizon temporal logic planning for dynamical systems. In: Proc. CDC, pp. 5997–6004. IEEE Press, Los Alamitos (2009)Google Scholar
  34. 34.
    Wongpiromsarn, T., Topcu, U., Murray, R.M.: Automatic synthesis of robust embedded control software. In: AAAI Spring Symposium on Embedded Reasoning: Intelligence in Embedded Systems (2010)Google Scholar
  35. 35.
    Wongpiromsarn, T., Topcu, U., Murray, R.M.: Receding horizon control for temporal logic specifications. In: Proc. HSCC. LNCS, Springer, Heidelberg (2010)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Uri Klein
    • 1
  • Amir Pnueli
    • 1
  1. 1.Courant Institute of Mathematical SciencesNew York UniversityNew YorkUSA

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