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Reaching Coverage Closure in Post-silicon Validation

  • Allon Adir
  • Amir Nahir
  • Avi Ziv
  • Charles Meissner
  • John Schumann
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6504)

Abstract

Obtaining coverage information in post-silicon validation is a difficult task. Adding coverage monitors to the silicon is costly in terms of timing, power, and area, and thus even if feasible, is limited to a small number of coverage monitors. We propose a new method for reaching coverage closure in post-silicon validation. The method is based on executing the post-silicon exercisers on a pre-silicon acceleration platform, collecting coverage information from these runs, and harvesting important test templates based on their coverage. This method was used in the verification of IBM’s POWER7 processor. It contributed to the overall high-quality verification of the processor, and specifically to the post-silicon validation and bring-up.

Keywords

Coverage Event Coverage Information Test Plan Stimulus Generation Coverage Hole 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Allon Adir
    • 1
  • Amir Nahir
    • 1
  • Avi Ziv
    • 1
  • Charles Meissner
    • 2
  • John Schumann
    • 2
  1. 1.IBM Research LaboratoryHaifaIsrael
  2. 2.IBM Server and Technology GroupAustinUSA

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