A Low-Area Yet Performant FPGA Implementation of Shabal

  • Jérémie Detrey
  • Pierrick Gaudry
  • Karim Khalfallah
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6544)


In this paper, we present an efficient FPGA implementation of the SHA-3 hash function candidate Shabal [7]. Targeted at the recent Xilinx Virtex-5 FPGA family, our design achieves a relatively high throughput of 2 Gbit/s at a cost of only 153 slices, yielding a throughput-vs.-area ratio of 13.4 Mbit/s per slice. Our work can also be ported to Xilinx Spartan-3 FPGAs, on which it supports a throughput of 800 Mbit/s for only 499 slices, or equivalently 1.6 Mbit/s per slice.

According to the SHA-3 Zoo website [1], this work is among the smallest reported FPGA implementations of SHA-3 candidates, and ranks first in terms of throughput per area.


SHA-3 Shabal low area FPGA implementation 


  1. 1.
  2. 2.
    Aumasson, J.P., Henzen, L., Meier, W., Phan, R.C.W.: SHA-3 proposal BLAKE (October 2008),
  3. 3.
    Baldwin, B., Byrne, A., Mark, H., Hanley, N., McEvoy, R.P., Pan, W., Marnane, W.P.: FPGA implementations of SHA-3 candidates: CubeHash, Grøstl, LANE, Shabal and Spectral Hash. In: 12th Euromicro Conference on Digital Systems Design, Architectures, Methods and Tools (DSD 2009), pp. 783–790. IEEE Computer Society, Patras (August 2009)CrossRefGoogle Scholar
  4. 4.
    Bertoni, G., Daemen, J., Peeters, M., Van Assche, G.: The Keccak sponge function family (April 2009),
  5. 5.
    Beuchat, J.L., Okamoto, E., Yamazaki, T.: A compact FPGA implementation of the SHA-3 candidate ECHO. Report 2010/364, Cryptology ePrint Archive (June 2010),
  6. 6.
    Beuchat, J.L., Okamoto, E., Yamazaki, T.: Compact implementations of BLAKE-32 and BLAKE-64 on FPGA. Report 2010/173, Cryptology ePrint Archive (April 2010),
  7. 7.
    Bresson, E., Canteaut, A., Chevallier-Mames, B., Clavier, C., Fuhr, T., Gouget, A., Icart, T., Misarsky, J.F., Naya-Plasencia, M., Paillier, P., Pornin, T., Reinhard, J.R., Thuillet, C., Videau, M.: Shabal, a submission to NIST’s cryptographic hash algorithm competition (October 2008),
  8. 8.
    Bulens, P., Kalach, K., Standaert, F.X., Quisquater, J.J.: FPGA implementations of eSTREAM phase-2 focus candidates with hardware profile. Report 2007/024, eSTREAM, ECRYPT Stream Cipher Project (January 2007),
  9. 9.
    Feron, R., Francq, J.: FPGA implementation of Shabal: Our first results (February 2010),
  10. 10.
    Gauravaram, P., Knudsen, L.R., Matusiewicz, K., Mendel, F., Rechberger, C., Schläffer, M., Thomsen, S.S.: Grøstl: A SHA-3 candidate (October 2008),
  11. 11.
    Jungk, B., Reith, S.: On FPGA-based implementations of Grøstl. Report 2010/260, Cryptology ePrint Archive (May 2010),
  12. 12.
    Jungk, B., Reith, S., Apfelbeck, J.: On optimized FPGA implementations of the SHA-3 candidate Grøstl. Report 2009/206, Cryptology ePrint Archive (May 2009),
  13. 13.
    Kobayashi, K., Ikegami, J., Matsuo, S., Sakiyama, K., Ohta, K.: Evaluation of hardware performance for the SHA-3 candidates using SASEBO-GII. Report 2010/010, Cryptology ePrint Archive (January 2010),
  14. 14.
    Long, M.: Implementing Skein hash function on Xilinx Virtex-5 FPGA platform (February 2009),
  15. 15.
    Lu, L., O’Neill, M., Swartzlander, E.: Hardware evaluation of SHA-3 hash function candidate ECHO (May 2009),
  16. 16.
    Naehrig, M., Peters, C., Schwabe, P.: SHA-2 will soon retire: The SHA-3 song. Journal of Craptology 7 (February 2010)Google Scholar
  17. 17.
    Namin, A.H., Hasan, M.A.: Hardware implementation of the compression function for selected SHA-3 candidates. Tech. Rep. 2009-28, Centre for Applied Cryptographic Research, University of Waterloo (July 2009),
  18. 18.
    Regenscheid, A., Perlner, R., Chang, S., Kelsey, J., Nandi, M., Paulu, S.: Status report on the first round of the SHA-3 cryptographic hash algorithm competition. Report NISTIR 7620, National Institute of Standards and Technology (September 2009),
  19. 19.
    Tillich, S.: Hardware implementation of the SHA-3 candidate Skein. Report 2009/159, Cryptology ePrint Archive (April 2009),
  20. 20.
    Xilinx: Spartan-3 generation FPGA user guide,
  21. 21.
    Xilinx: Spartan-6 FPGA Configurable Logic Block user guide,
  22. 22.
    Xilinx: Virtex-5 FPGA data sheet: DC and switching characteristics,
  23. 23.
  24. 24.
    Xilinx: Virtex-6 FPGA Configurable Logic Block user guide,

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Jérémie Detrey
    • 1
  • Pierrick Gaudry
    • 1
  • Karim Khalfallah
    • 2
  1. 1.CARAMEL project-team, LORIAINRIA / CNRS / Nancy UniversitéVandœuvre-lès-Nancy CedexFrance
  2. 2.Laboratoire de cryptographie et composantsSGDSN / ANSSIParis 07France

Personalised recommendations