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A Low-Area Yet Performant FPGA Implementation of Shabal

  • Jérémie Detrey
  • Pierrick Gaudry
  • Karim Khalfallah
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6544)

Abstract

In this paper, we present an efficient FPGA implementation of the SHA-3 hash function candidate Shabal [7]. Targeted at the recent Xilinx Virtex-5 FPGA family, our design achieves a relatively high throughput of 2 Gbit/s at a cost of only 153 slices, yielding a throughput-vs.-area ratio of 13.4 Mbit/s per slice. Our work can also be ported to Xilinx Spartan-3 FPGAs, on which it supports a throughput of 800 Mbit/s for only 499 slices, or equivalently 1.6 Mbit/s per slice.

According to the SHA-3 Zoo website [1], this work is among the smallest reported FPGA implementations of SHA-3 candidates, and ranks first in terms of throughput per area.

Keywords

SHA-3 Shabal low area FPGA implementation 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Jérémie Detrey
    • 1
  • Pierrick Gaudry
    • 1
  • Karim Khalfallah
    • 2
  1. 1.CARAMEL project-team, LORIAINRIA / CNRS / Nancy UniversitéVandœuvre-lès-Nancy CedexFrance
  2. 2.Laboratoire de cryptographie et composantsSGDSN / ANSSIParis 07France

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