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High Performance Programmable FPGA Overlay for Digital Signal Processing

  • Séamas McGettrick
  • Kunjan Patel
  • Chris Bleakley
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6578)

Abstract

In this paper we investigate the use of a programmable overlay to increase the performance of variable DSP workloads executing on FPGAs. The overlay approach reduces reconfiguration time and provides fast processing. The overlay was implemented on a Virtex-5 110Lx FPGA and its performance was compared with that of a conventional GPP, DSP processor and custom FPGA implementation. It is found that both FPGA based architectures outperform the GPP and DSP processor implementations. Taking into account reconfiguration the programmable overlay was found to outperform the custom FPGA implementation for small and medium data sets. On a 255 FIR filter it was shown that the programmable overlay performed better than the custom hardware on all data sets below 40 million entries.

Keywords

Coarse Grained Reconfigurable Arrays (CGRA) Field Programmable Gate Array (FPGA) overlay Reconfigurable computing Fixed point 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Séamas McGettrick
    • 1
  • Kunjan Patel
    • 1
  • Chris Bleakley
    • 1
  1. 1.UCD Complex and Adaptive Systems Laboratory, UCD School of Computer Science and InformaticsUniversity College DublinDublin 4Ireland

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