Architecture of an Adaptive Test System Built on FPGAs
- Cite this paper as:
- Sachße J., Wuttke HD., Ostendorff S., Meza Escobar J.H. (2011) Architecture of an Adaptive Test System Built on FPGAs. In: Berekovic M., Fornaciari W., Brinkschulte U., Silvano C. (eds) Architecture of Computing Systems - ARCS 2011. ARCS 2011. Lecture Notes in Computer Science, vol 6566. Springer, Berlin, Heidelberg
This paper describes an FPGA based test system, designed to improve current board level test methods such as boundary scan. The design of the system architecture is based on a layer concept that provides important advantages for its flexibility. This makes it possible to reconfigure and automatically generate the test system determined by the board’s properties and the specific test algorithms. The principal system components are a soft-processor equipped with debug and communication functions, and co-processing units built from component models. The system architecture and its relation to the layer concept are presented, mentioning basic properties such as FPGA vendor independency and JTAG compatibility.
Keywordsadaptive test systems reconfigurable hardware and software automatic system generation soft-processor field programmable gate arrays
Unable to display preview. Download preview PDF.