Architecture of an Adaptive Test System Built on FPGAs

  • Jörg Sachße
  • Heinz-Dietrich Wuttke
  • Steffen Ostendorff
  • Jorge H. Meza Escobar
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6566)


This paper describes an FPGA based test system, designed to improve current board level test methods such as boundary scan. The design of the system architecture is based on a layer concept that provides important advantages for its flexibility. This makes it possible to reconfigure and automatically generate the test system determined by the board’s properties and the specific test algorithms. The principal system components are a soft-processor equipped with debug and communication functions, and co-processing units built from component models. The system architecture and its relation to the layer concept are presented, mentioning basic properties such as FPGA vendor independency and JTAG compatibility.


adaptive test systems reconfigurable hardware and software automatic system generation soft-processor field programmable gate arrays 


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE Std. 1149.1-2001 (R2008) (Revision of IEEE Std 1149.1-1990) (2008)Google Scholar
  2. 2.
    Wallace, D.: Using the JTAG Interface as a General-Purpose Communication Interface. Silicon and Software Systems (2005)Google Scholar
  3. 3.
    Devadze, S., Jutman, A., Aleksejev, I., Ubar, R.: Turning JTAG inside out for Fast Extended Test Access. In: 10th IEEE Latin America Test Workshop (LATW 2009), Rio de Janeiro, Brazil, March 2-5 (2009)Google Scholar
  4. 4.
    Nadeau-Dostie, B., et al.: An embedded technique for At-speed Interconnect Testing. In: International Test Conference (ITC 1999), Atlantic City, NJ, USA, September 28-30 (1999)Google Scholar
  5. 5.
    Park, S., Kim, T.: A new IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects. In: Design, Automation and Test in Europe (DATE 2000), Paris, France, March 27-30 (2000)Google Scholar
  6. 6.
    Jutman, A., Devadze, S., Aleksejev, I.: BS2VHDL and other Embedded Techniques for Boundary Scan Test Acceleration. In: Nordic Test Forum 2009, Stockholm, Sweden, December 1-2 (2009)Google Scholar
  7. 7.
    Jutman, A.: At-speed on-chip diagnosis of board-level interconnect faults. In: 9th IEEE European Test Symposium (ETS 2004), Ajaccio, Corsica, France, May 23-26 (2004)Google Scholar
  8. 8.
    Ostendorff, S., Wuttke, H.-D., Sachße, J., Köhler, S.: A new approach for adaptive failure diagnostics based on emulation test. In: Design, Automation and Test in Europe (DATE 2010), Dresden, Germany, March 8-12 (2010)Google Scholar
  9. 9.
    GÖPEL electronic, Combining Boundary Scan and JTAG Emulation for Advanced Structural Test and Diagnostics, White Paper (May 2009) Google Scholar
  10. 10.
    Asset, Intertech. Combine Boundary Scan with CPU Emulation to Extend Test-Coverage, White Paper (May 2004)Google Scholar
  11. 11.
    Devadze, S., Jutman, A., Aleksejev, I., Ubar, R.: Fast extended test access via JTAG and FPGAs. In: International Test Conference (ITC 2009), Austin, Texas, USA, November 1-6 (2009)Google Scholar
  12. 12.
    Ostendorff, S., Wuttke, H.-D., Sachße, J., Meza Escobar, J.-H.: Test Pattern Dependent FPGA Based System Architecture for JTAG Tests. In: The 5th International Conference on Systems (ICONS 2010), Menuires, France, April 11-16 (2010)Google Scholar
  13. 13.

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Jörg Sachße
    • 1
  • Heinz-Dietrich Wuttke
    • 1
  • Steffen Ostendorff
    • 1
  • Jorge H. Meza Escobar
    • 1
  1. 1.Integrated Communication Systems GroupIlmenau University of TechnologyIlmenauGermany

Personalised recommendations