Architecture of an Adaptive Test System Built on FPGAs

  • Jörg Sachße
  • Heinz-Dietrich Wuttke
  • Steffen Ostendorff
  • Jorge H. Meza Escobar
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6566)

Abstract

This paper describes an FPGA based test system, designed to improve current board level test methods such as boundary scan. The design of the system architecture is based on a layer concept that provides important advantages for its flexibility. This makes it possible to reconfigure and automatically generate the test system determined by the board’s properties and the specific test algorithms. The principal system components are a soft-processor equipped with debug and communication functions, and co-processing units built from component models. The system architecture and its relation to the layer concept are presented, mentioning basic properties such as FPGA vendor independency and JTAG compatibility.

Keywords

adaptive test systems reconfigurable hardware and software automatic system generation soft-processor field programmable gate arrays 

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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Jörg Sachße
    • 1
  • Heinz-Dietrich Wuttke
    • 1
  • Steffen Ostendorff
    • 1
  • Jorge H. Meza Escobar
    • 1
  1. 1.Integrated Communication Systems GroupIlmenau University of TechnologyIlmenauGermany

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