A Learning-Based Approach to the Automated Design of MPSoC Networks
Many embedded computing platforms are highly specialised towards a given task and, consequently, sacrifice generality for high performance and energy efficiency at low cost. It is commonly accepted that integrating multiple processor cores on the same chip is the most promising way of delivering a high level of processing power under tight energy and cost constraints. Whereas the customisation of individual processing elements to particular tasks such as DSP or multimedia functions is a well-studied problem, the specialisation of application-specific on-chip and off-chip interconnects between processing elements has been largely neglected.
In this paper we explore the design space of a tree-based network on chip of a synthesisable application-specific MPSoC. We empirically deduce the optimal network configurations, in terms of runtime and energy consumption, for a range of benchmark workloads. We present a machine learning approach that is able to predict optimal, or near-optimal, network-on-chip configurations for a new and as-yet-unseen workload. This new approach to automated NoC design yields designs that are, on average, within 9% of optimal design for the given workload. Moreover, the model predicts network configurations based on sample data from a single profiling run of the new application on a reference platform, providing the answer up to 280 times faster than an exhaustive search.
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