Compiler-Assisted Selection of a Software Transactional Memory System

  • Martin Schindewolf
  • Alexander Esselson
  • Wolfgang Karl
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6566)

Abstract

With the advent of Transactional Memory, a multitude of Software Transactional Memory (STM) systems evolved. Often, the programmer sets key parameters of an STM system at compile time. The performance of the application depends on choosing the right parameters. Unfortunately, programmers do not always know the application characteristic to decide on a profound basis. As a consequence, the application may run longer than necessary. Thus, we propose MAPT, which uses static information to guide the programmer to select an STM property. In particular, MAPT assists the programmer to select the resolution of the conflict detection scheme. This paper presents MAPT, its integration in the Low Level Virtual Machine compiler framework, and results from the evaluation with test cases and two STAMP benchmarks.

Keywords

Software Transactional Memory Granularity Compiler Assistance LLVM Heuristic 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Intel transactional memory compiler and runtime application binary interface (November 2008), http://software.intel.com/file/8097
  2. 2.
    Draft specification of transactional language constructs for c++ (August 2009), http://software.intel.com/file/21569
  3. 3.
    Baek, W., Minh, C.C., Trautmann, M., Kozyrakis, C., Olukotun, K.: The opentm transactional application programming interface. In:16th International Conference on Parallel Architecture and Compilation Techniques, PaCT 2007, September 15-19 , pp. 376–387 (2007)Google Scholar
  4. 4.
    Cao Minh, C., Chung, J., Kozyrakis, C., Olukotun, K.: STAMP: Stanford transactional applications for multi-processing. In: IISWC 2008: Proceedings of The IEEE International Symposium on Workload Characterization (September 2008)Google Scholar
  5. 5.
    Christie, D., Chung, J.-W., Diestelhorst, S., Hohmuth, M., Pohlack, M., Fetzer, C., Nowack, M., Riegel, T., Felber, P., Marlier, P., Rivière, E.: Evaluation of amd’s advanced synchronization facility within a complete transactional memory stack. In: EuroSys 2010: Proceedings of the 5th European Conference on Computer systems, pp. 27–40. ACM, New York (2010)Google Scholar
  6. 6.
    Lattner, C., Adve, V.: Llvm: A compilation framework for lifelong program analysis & transformation. In: International Symposium on Code Generation and Optomization, CGO 2004 (March 2004)Google Scholar
  7. 7.
    Damron, P., Fedorova, A., Lev, Y., Luchangco, V., Moir, M., Nussbaum, D.: Hybrid transactional memory. In: ASPLOS-XII: Proceedings of the 12th International Conference on Architectural Support for Programming Languages and Operating Systems, pp. 336–346. ACM, New York (2006)CrossRefGoogle Scholar
  8. 8.
    Dice, D., Shalev, O., Shavit, N.: Transactional locking ii. In: Dolev, S. (ed.) DISC 2006. LNCS, vol. 4167, pp. 194–208. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  9. 9.
    Felber, P., Fetzer, C., Müller, U., Riegel, T., Süßkraut, M., Sturzrehm, H.: Transactifying applications using an open compiler framework. In: Workshop on Transactional Computing, TRANSACT (August 2007)Google Scholar
  10. 10.
    Felber, P., Fetzer, C., Riegel, T.: Dynamic performance tuning of word-based software transactional memory. In: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 237–246 (2008) ISBN:978-1-59593-795-7Google Scholar
  11. 11.
    Herlihy, M., Moss, J.E.B.: Transactional Memory: Architectural Support For Lock-free Data Structures. In: Proceedings of the 20th Annual International Symposium on Computer Architecture, pp. 289–300. IEEE, Los Alamitos (1993)Google Scholar
  12. 12.
    Herlihy, M., Moss, J.E.B.: Transactional memory: architectural support for lock-free data structures. SIGARCH Comput. Archit. News 21(2), 289–300 (1993)CrossRefGoogle Scholar
  13. 13.
    Hill, M.D., Hower, D., Moore, K.E., Swift, M.M., Volos, H., Wood, D.A.: A case for deconstructing hardware transactional memory systems. In: Programming Models for Ubiquitous Parallelism. Dagstuhl Seminar Proceedings, vol. 07361 (2007)Google Scholar
  14. 14.
    IBM: Ibm xl c/c++ for transactional memory for aix (May 2008), http://www.alphaworks.ibm.com/tech/xlcstm
  15. 15.
    Intel Corporation: Technologies for Measuring Software Performance: VTune Analyzers (2003), White paperGoogle Scholar
  16. 16.
    Larus, J.R., Rajwar, R.: Transactional Memory. Morgan Claypool Publishers, San Francisco (2007)Google Scholar
  17. 17.
    Lattner, C.: Macroscopic Data Structure Analysis and Optimization. Ph.D. thesis, Computer Science Department, University of Illinois at Urbana-Champaign (2002)Google Scholar
  18. 18.
    Lev, Y., Moir, M., Nussbaum, D.: PhTM: Phased transactional memory. In: TRANSACT 2007: 2nd Workshop on Transactional Computing (August 2007), http://labs.oracle.com/scalable/pubs/TRANSACT2007-PhTM.pdf
  19. 19.
    Lev, Y., Luchangco, V., Marathe, V., Moir, M., Nussbaum, D., Olszewski, M.: Anatomy of a scalable software transactional memory. In: TRANSACT 2009: Workshop on Transactional Computing (February 2009)Google Scholar
  20. 20.
    Menon, V., Balensiefer, S., Shpeisman, T., Adl-Tabatabai, A.-R., Hudson, R.L., Saha, B., Welc, A.: Practical weak-atomicity semantics for java stm. In: SPAA 2008: Proceedings of the Twentieth Annual Symposium on Parallelism in Algorithms and Architectures, pp. 314–325. ACM, New York (2008)CrossRefGoogle Scholar
  21. 21.
    Milovanović, M., Ferrer, R., Gajinov, V., Unsal, O.S., Cristal, A., Ayguadé, E., Valero, M.: Multithreaded software transactional memory and openmp. In: MEDEA 2007: Proceedings of the 2007 Workshop on MEmory Performance, pp. 81–88. ACM, New York (2007)Google Scholar
  22. 22.
    Oechslein, B.: Statische WCET-Analyse von LLVM-Bytecode. Master’s thesis, Friedrich-Alexander-Universität Erlangen-Nürnberg (August 2008), http://www4.informatik.uni-erlangen.de/~benjamin/documents/Statische.WCET.Analyse.von.LLVM.Bytecode.pdf
  23. 23.
    Saha, B., Adl-Tabatabai, A.-R., Hudson, R.L., Minh, C.C., Hertzberg, B.: Mcrt-stm: a high performance software transactional memory system for a multi-core runtime. In: PPoPP 2006: Proceedings of the Eleventh ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, pp. 187–197. ACM, New York (2006)Google Scholar
  24. 24.
    Schindewolf, M., Cohen, A., Karl, W., Marongiu, A., Benini, L.: Towards transactional memory support for gcc. In: GROW 2009: First International Workshop on GCC Research Opportunities (January 2009), http://www.doc.ic.ac.uk/~phjk/GROW09/papers/03-Transactions-Schwindewolf.pdf
  25. 25.
    Schindewolf, M., Karl, W.: Investigating compiler support for software transactional memory. In: Proceedings of ACACES 2009 Poster Abstracts: Advanced Computer Architecture and Compilation for Embedded Systems, pp. 89–92. Academia Press, Ghent (July 2009)Google Scholar
  26. 26.
    Wang, C., Chen, W.Y., Wu, Y., Saha, B., Adl-Tabatabai, A.R.: Code generation and optimization for transactional memory constructs in an unmanaged language. In: CGO 2007: Proceedings of the International Symposium on Code Generation and Optimization, pp. 34–48. IEEE Computer Society, Washington (2007)Google Scholar
  27. 27.
    Yen, L., Bobba, J., Marty, M.R., Moore, K.E., Volos, H., Hill, M.D., Swift, M.M., Wood, D.A.: Logtm-se: Decoupling hardware transactional memory from caches. In: IEEE 13th International Symposium on High Performance Computer Architecture, HPCA 2007, pp. 261–272 (February 2007)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  • Martin Schindewolf
    • 1
  • Alexander Esselson
    • 1
  • Wolfgang Karl
    • 1
  1. 1.Institute of Computer Science & Engineering (ITEC)Karlsruhe Institute of Technology (KIT)KarlsruheGermany

Personalised recommendations