Monolithic Single-Photon Avalanche Diodes: SPADs

Part of the Springer Series in Optical Sciences book series (SSOS, volume 160)


The art of creating monolithic single-photon photodetectors is a mix of design skills and device physics knowledge, and it requires an understanding of the mechanisms underlying single-photon detection in highly complex integrated systems. This chapter begins with the fundamentals of avalanching, the basics for integration of avalanche photodiodes operating in Geiger-mode, and the issues associated with large arrays. We outline the techniques that made it possible to integrate single-photon detectors in standard CMOS processes, and to design compact ancillary electronics for operating and reading pixels based on these devices. Finally, we present a description of several readout architectures designed for massive arrays of single-photon detectors. A discussion of future trends in the context of the most advanced applications in various fields of research concludes this chapter. The art of creating monolithic single-photon photodetectors is a mix of design skills and device physics knowledge, and it requires an understanding of the mechanisms underlying single-photon detection in highly complex integrated systems. This chapter begins with the fundamentals of avalanching, the basics for integration of avalanche photodiodes operating in Geiger-mode, and the issues associated with large arrays. We outline the techniques that made it possible to integrate single-photon detectors in standard CMOS processes, and to design compact ancillary electronics for operating and reading pixels based on these devices. Finally, we present a description of several readout architectures designed for massive arrays of single-photon detectors. A discussion of future trends in the context of the most advanced applications in various fields of research concludes this chapter.

7.1 A Brief Historical Perspective

Solid-state single-photon detectors have existed for decades and, while several flavors of solid-state detectors exist in various technologies and ranges of operation, from cryogenic to room temperature detectors, silicon avalanche photodiodes (APDs) have emerged as the most versatile and easy to use among them [1]. A class of APDs operating above breakdown, in so-called Geiger-mode and known as single-photon avalanche diodes (SPADs) or Geiger-mode APDs (GAPDs), is of particular interest due to their amenability to integration in planar silicon processes in combination with conventional digital and analog circuitries. The first SPADs implemented in a planar technology have emerged relatively recently [2, 3]. But, while the physics of solid-state SPADs is well understood [4], it is only with the advent of devices integrated in conventional complementary metal–oxide–semiconductor (CMOS) processes [5] that the evolution onto smaller and smaller feature sizes has rapidly advanced to the point that it has now become possible to envision large imaging systems based on SPADs. It is on these systems that this chapter will focus.

7.2 Fundamental Mechanisms

The models covered in the following sections are based on [6, 1, 4].

7.2.1 SPAD Structure and Operation

A SPAD is essentially a p–n junction biased above breakdown and equipped with avalanche quenching and recharge mechanisms. When a photon is incident on the diode, an avalanche may be triggered. The quenching circuitries stop the avalanche thus preventing the destruction of the device, while the recharge circuitries prepare the SPAD for the next detection. When many engineers think of a p–n junction’s I–V curve, they think of the steady-state curve shown in Fig. 7.1. In this curve, there are three main regions: forward, reverse, and breakdown. Breakdown occurs when the electric field is strong enough that accelerated carriers cause ionization, that is the creation of mobile electron–hole pairs. The breakdown region can be further subdivided into the linear and Geiger-mode regions. In the linear region, the electrical field is strong enough to cause significant ionization through free electrons, but not through holes of the same energy. The region is named for the expected linear gain per injected electron. In Geiger-mode, named after its similarity to the operation of a Geiger counter, the electric field is so strong that both electrons and holes cause significant ionization. In Geiger-mode, the current is limited only by the space-charge phenomenon, which is the electric field drop from the charge of carriers currently moving across the depletion region of the diode.
Fig. 7.1

I–V characteristics shown for a p–n junction (left) and a SPAD in a standard passive quenching scheme (right)

Quantitatively, to be in Geiger-mode, the expected number of created carriers from ionization must exceed one. For a one-dimensional junction ranging from z0 to z1, and with \(\bar{\alpha }\) (units cm − 1) representing the mean ionization rate in a semiconductor with equal electron and hole ionization coefficients, the condition to be in Geiger-mode is:
$${\int \nolimits \nolimits }_{{z}_{0}}^{{z}_{1} }\bar{\alpha }\,\mathrm{d}z > 1.$$
The voltage sufficient to meet this condition for a particular p–n junction is called the breakdown voltage, and the excess bias is the voltage applied above this voltage. In this chapter, the breakdown voltage will be considered positive, not negative. Readers unfamiliar with this terminology should be wary of the signs of all voltages. In the Geiger-mode regime, a single carrier in the depletion region can create an enormous current. The location of the carrier in the depletion region can change the chance that it triggers as avalanche, as many diodes have a nonuniform electric field. In particular, one-sided p–n junctions will have a linear electric field. In diodes with a nonuniform electric field, the portion of the depletion region where at least 95% of the ionization takes place is termed the multiplication region, also called the avalanche region in some texts [6]. This spatial region will not be called the avalanche region, as this term is used in this text for regions of the diode under avalanche. Carriers generated in the depletion region but not the multiplication region will drift either toward or away from the multiplication region depending on their charge and the p–n junction’s doping levels. Due to the larger ionization coefficients of electrons compared to holes in many semiconductors, it is almost always preferable to have more electrons than holes drift toward the multiplication region. The avalanche’s originating carrier can be the result of an electron–hole pair caused by a single photon, hence the term SPAD [6].

If a SPAD is operating at the steady-state value on the p–n junction’s I–V curve, in practice it will heat up and be destroyed. However, the I–V curve of a SPAD coupled to quenching circuitry, also called ballast circuitry, has very different characteristics from a p–n junction’s I–V curve. This section will cover the dynamics of an avalanche assuming a large resistance is placed in series with the diode. This is known as passive quenching, and produces the I–V curve shown in Fig. 7.1 when the diode is under low light. This I–V curve is not a true steady-state curve as the location on the I–V curve depends on whether an avalanche is occurring.

The I–V curve of the SPAD and ballast circuitry is dependent on the amount of light impinging on the SPAD. Under moderate to no light, the curve has four phases, each with distinct dominating factors: idle, buildup, quenching and spread, and recharge. The first phase, an unstable, idle state, is a quasi-steady-state condition that occurs when no free carriers are near the p–n junction itself. The second phase, avalanche buildup, is the result of positive feedback from ionization until negative feedback from the space-charge phenomena balances carrier creation from ionization. The third phase, spread and quenching, is the result of the multiplication- or photon-assisted spread of the avalanche region and global, negative feedback from the quenching circuitry. In the final phase, recharge, the quenching circuitry restores the diode to the conditions in the first phase. A basis for the triggering sources, noise and light, is also examined in detail.

When a SPAD is placed under very intense light, the negative feedback in the recharge phase does not have sufficient time to restore the diode to its idle state. This creates a steady-state value close to the value on a p–n junction’s I–V curve. In SPAD-based systems, especially communication systems, it may be necessary to ensure that the SPADs are not in this state.

7.2.2 Idle State and Avalanche Buildup

A SPAD is idle when there are no free carriers in the depletion region and the excess bias is as desired. The large charge separation has created a very high electric field in the middle portion of the SPAD, but without any free carriers ionization cannot occur. The charge separation also contributes a parasitic capacitance effect, though other capacitances from the guard ring and transistor gates may have a larger effect on the parasitic capacitance than the depletion region’s charge separation. The SPAD will remain in this state until an event, such as the interaction with an incident photon, injects an electron–hole pair into or near the depletion region.

When carriers are injected into the depletion region, there are several possibilities. The first possibility is that all carriers drift out of the depletion region without causing ionization. The carriers might even drift through portions of the multiplication region without ionizing. The second possibility is that ionizations of the initial or ionization-generated carriers do occur, but all carriers are swept out of the depletion region without reaching sufficient number to trigger an avalanche. If a photon caused the initial pair’s creation, then this photon will not be detected. To give a nuanced view, there is always the possibility that any number of ionization-generated carriers could fail to trigger an avalanche; however once the number of carriers reaches a certain threshold, this border case’s probability is so small that it can be ignored. Finally, enough ionization can occur that other processes will begin to govern the avalanche dynamics. The buildup phase of an avalanche occurs from when the initial electron–hole pair is injected to when the space-charge phenomena causes the excess bias across a particular area of the diode to drop to nearly zero. The drop in excess bias will create a balance between carrier generation from ionization and carrier loss from drift. Due to parasitic capacitance effects, in general the applied voltage across the diode does not change greatly during the buildup phase.

The initial ionization occurs in a relatively small area. There is always the possibility that diffusion will cause carriers to move substantial distances; however, the probability of this is so low that it can be ignored in practice. Based on the local conditions of positive feedback from ionization and negative feedback from carrier drift, the number of free carriers c in a small portion of the diode is approximated analytically by equation:
$$\frac{\mathrm{d}c} {\mathrm{d}t} = c\left ( \frac{1} {{\tau }_{\mathrm{p}}} - \frac{1} {{\tau }_{\mathrm{n}}}\right ),$$
where τp relates to the positive feedback from ionization, while τn relates to the negative feedback from carrier drift. Both terms will also change as the excess bias varies due to the space-charge phenomena. Multiple ways of deriving τp and τn exist: the analysis here is based after [1], as the use of the same ionization coefficients for electrons and holes simplifies the derivation without essentially changing the results. For an analysis with different ionization rates for electrons and holes, we refer to [4].
For a small portion of the diode, assuming that electron and hole concentrations can be written as a function of depth, n(z, t) and p(z, t), respectively, with carriers traveling at the saturation velocity vs, the current density je(z, t) from electrons is given by:
$${j}_{\mathrm{e}}(z,t) = -(q \cdot {v}_{\mathrm{s}} \cdot n(z,t)),$$
where q is the electron charge. In a small time Δt, the increase in electron concentration due to ionization will be the distance each carrier travels (units cm) multiplied by the ionization rate (units cm − 1) and the carrier concentration (units cm − 3), which is \(({v}_{\mathrm{s}}\Delta t) \cdot (\bar{\alpha }) \cdot (n(z,t) + p(z,t))\). This expression is the basis for the carrier generation term in the continuity equation. The continuity equation for electrons, which governs the change in electron concentration, will be
$$\frac{\mathrm{d}n(z,t)} {\mathrm{d}t} = \frac{1} {q} \frac{\mathrm{d}{j}_{\mathrm{e}}(z,t)} {\mathrm{d}z} +{v}_{\mathrm{s}}\bar{\alpha }(n(z,t)+p(z,t)) = -{v}_{\mathrm{s}}\frac{\mathrm{d}n(z,t)} {\mathrm{d}z} +{v}_{\mathrm{s}}\bar{\alpha }(n(z,t)+p(z,t)),$$
with a use of (7.3) in simplifying the expression. Similarly, for holes
$$\frac{\mathrm{d}p(z,t)} {\mathrm{d}t} = {v}_{\mathrm{s}}\frac{\mathrm{d}p(z,t)} {\mathrm{d}z} + {v}_{\mathrm{s}}\bar{\alpha }(n(z,t) + p(z,t)).$$
Since the total carrier concentration is a sum of the electron and hole concentrations, c(z, t) = n(z, t) + p(z, t), (7.4) and (7.5) can be combined to yield:
$$\frac{\mathrm{d}c(z,t)} {\mathrm{d}t} = {v}_{\mathrm{s}}\left (\frac{\mathrm{d}p(z,t)} {\mathrm{d}z} -\frac{\mathrm{d}n(z,t)} {\mathrm{d}z} \right ) + 2\bar{\alpha }{v}_{\mathrm{s}}c(z,t).$$
For a p–n junction with its depletion region’s p-doped edge at z0 and the depletion region’s n-doped edge at z1 with total depletion region width zd = z1 − z0, the expression for the carrier concentration can be integrated in the spatial dimension z with the following boundary conditions: there is a negligible electron concentration at the edge of the depletion region on the p-doped side of the junction, n(z0, t) = 0; there is a negligible hole concentration at the edge of the depletion region on the n-doped side of the junction, p(z1, t) = 0; and there are identical hole and electron concentrations at opposite sides of the diode, which are equal to the carrier concentration, n(z1, t) = p(z0, t) = c(t) = 0. Thus, the carrier concentration will change over time as:
$$\begin{array}{rlrlrl} \begin{array}{rlrlrl} ({z}_{1} - {z}_{0})\dfrac{\mathrm{d}c(t)} {\mathrm{d}t} = -2c(t){v}_{\mathrm{s}} + 2\bar{\alpha }{v}_{\mathrm{s}}c(t)({z}_{1} - {z}_{0}) \\ \dfrac{\mathrm{d}c(t)} {\mathrm{d}t} = 2c(t)\left ({v}_{\mathrm{s}}\bar{\alpha } - \dfrac{{v}_{\mathrm{s}}} {{z}_{\mathrm{d}}}\right )\qquad \quad \quad \ \ \ \end{array}. & &\end{array}$$
The form of (7.2) is identical to (7.7). If the variables α and zd were constant, then (7.7) would absurdly imply that the carrier concentration would build forever. These variables are actually functions of the excess bias, which is related to the carrier concentration by the space-charge phenomena. The depletion region width zd will change based on the applied bias. We will assume that the excess bias is small enough that a voltage drop from Vop to Vbd does not change this distance, which is a valid assumption for the standard operating conditions of most planar silicon diodes. Because the space-charge resistance times unit area ARsc is a function of depletion region width, this expression may be taken as constant, too.
While the depletion region width does not change appreciably, the same cannot be said of the ionization rate. The mean ionization rate as a function of the electric field is:
$$\bar{\alpha }(\xi ) = {A}_{\alpha }\exp \left (-{\left (\alpha /\left \vert \xi \right \vert \right )}^{m}\right ),$$
where the variables m and Aα (not to be confused with the area, A) are constants that depend on the material, and in silicon they have been measured as 1 and 107 cm − 1 [7]. The variable α can be found by solving for equality in (7.1), the breakdown condition. The electric field in a p–n junction will be a function of the applied voltage V, turning ξ into ξ(V ). For current I(t) = j(t)A = c(t)vsqA, the applied voltage will vary as \(V = {V }_{\mathrm{op}} - I\quad {R}_{\mathrm{SC}} = {V }_{\mathrm{op}} - c(t){\mathit{qv}}_{\mathrm{s}}({\mathit{AR}}_{\mathrm{sc}})\). Thus, the ionization rate will be:
$$\bar{\alpha }(\xi (V )) = {A}_{\alpha } \cdot \exp \left (-{\left (\alpha /\left \vert \xi (V )\right \vert \right )}^{m}\right ) = {A}_{\alpha } \cdot \exp \left (-{\left (\alpha /\left \vert \xi ({V }_{\mathrm{op}} - c(t){\mathit{qv}}_{\mathrm{s}}({\mathit{AR}}_{\mathrm{sc}}))\right \vert \right )}^{m}\right ).$$
In a one-sided junction, the electric field will vary as the square root of the applied voltage, and this expression can be further reduced to:
$$\bar{\alpha }(c(t)) = {z}_{\mathrm{d}}{A}_{\alpha }^{2} \cdot \exp \left (-{\left ( \frac{{V }_{\mathrm{bd}}} {{V }_{\mathrm{op}} - c(t){\mathit{qv}}_{\mathrm{s}}({\mathit{AR}}_{\mathrm{sc}})}\right )}^{1/2}\right ).$$
Equations (7.7) and (7.10) give sufficient information to generate a differential equation governing the behavior of c(t) for the initial buildup stage in a small portion of the diode, with boundary conditions given by the time of the electron–hole pair injection. For a single-photon generating an electron–hole pair at time 0, the boundary conditions are c(t) = 0 cm − 3 for t < 0 and c(0) = 2 cm − 3.

The given analysis assumes deterministic generation rates. In reality ionization is a statistical process, with uncertainty around the deterministic “average” solution. The ionization statistics during the buildup phase are known to contribute significant jitter to the timing uncertainty of the photon’s arrival. Increasing the voltage threshold for determining the avalanche onset will increase the timing uncertainty, with the best jitter achieved with either a low voltage threshold or current-based approach [2, 8].

Unless the avalanche onset can be determined with some other technique, the statistics of ionization will set a limit on the timing uncertainty achievable with SPADs. Higher breakdown voltages, lower doping and smaller parasitic capacitances will lower this jitter.

7.2.3 Quench, Spread, and Recharge

Two modes for quenching and recharge exist: active and passive. In active mode, active circuitries are used to control the process. In passive mode, the avalanche current is passively controlling the process by way of a ballast resistive device. The literature on the subject is extensive, and it is beyond the scope of this chapter to describe it further [9]. We describe hereafter only the mechanisms at device level underlying quenching.

During the initial phase of the avalanche, positive feedback in a local portion of the diode rapidly increases the carrier concentration until the space-charge phenomena indirectly stops the process. After this initial phase, the excess bias across the diode begins to decrease as the parasitic capacitance and quenching circuitry increase in applied voltage. Unlike in the buildup phase, when the applied voltage across the SPAD did not change greatly, in this phase the applied voltage will drop below the breakdown voltage, quenching the avalanche. Depending upon the SPAD’s characteristics, the spread of the avalanche in the planar directions may or may not play an important role in quenching. The avalanche spreads via both multiplication-assisted and photon-assisted processes. Photon-assisted spreading occurs from photons generated by recombination [9]. Multiplication-assisted spreading occurs from carrier diffusion in the planar directions [10]. Photon-assisted spreading is known to be dominant in large diodes, with multiplication-assisted processes dominating in smaller diodes.

Multiplication-assisted spreading is a process that combines positive feedback with diffusion, being governed by the equation:
$$\frac{\partial c(x,y)} {\partial t} = D{\nabla }^{2}c(x,y) + \frac{c(x,y)} {\tau (x,y)}.$$
In (7.11), c(x, y) is the free carrier concentration at a particular position, D is the diffusion coefficient of carriers in the planar direction, and τ is the same time constant presented for the buildup phase in (7.7) earlier. This differential equation can be solved numerically with an FEM model of a SPAD, such as the one shown in Fig. 7.2. The spreading speed of the avalanche is experimentally known to be \({v}_{\mathrm{s}} = 2\sqrt{D/\tau }\). In a planar silicon diode with D estimated at 15 cm2 ∕ s and τ = 10 ps, the spreading velocity is 2. 5 ×106 cm∕s. This is slightly below 25% of the saturation velocity of carriers in silicon at a similar temperature, though the τ value is a bit small compared to the expected value in many diodes. As the applied voltage decreases due to interactions with the quenching circuitry, the τ value will also increase, causing the spreading speed to be reduced.
Fig. 7.2

Diode models of a single diode (center) or a single diode split into multiple diodes (right) are shown for a p–n + junction. The current source and resistance should be exchanged for a p + –n diode, with the direction of the current source remaining the same

In a small planar diode, the avalanche will spread across the entire diode before quenching begins to occur. Whether or not a diode falls into this category will also depend on the parasitic capacitance, as large capacitances will allow more spreading before the avalanche can be sensed. In diodes that have the avalanche spread across the entire diode before sizeable quenching occurs, (7.7) and (7.10) with V as a function of time can also be used to describe the quenching of the avalanche. In (7.10), the variable V must be modified to account for changes in the applied voltage across the diode, including the effects of the parasitic capacitance and quenching circuitry.

For larger diodes, the quenching and spread cannot be decoupled. The spread and quenching will occur at the same time, and the observed voltage waveform may even vary as a function of initiation position or number of simultaneous initiations, giving rise to position-sensitive and photon-number-resolving SPADs. These diodes can be modeled as a finite number of smaller diodes, with the carrier concentration within a particular diode governed by (7.7), (7.10), and (7.11). Eventually, the avalanche will need to be completely quenched. The avalanche can be considered to have quenched when the number of free carriers in the multiplication region reaches some small number. An inductance-like component, which is caused by the inertia given to charges in the depletion region, aids in ensuring that the applied voltage eventually falls below the breakdown voltage. At this point in time, the excess bias across the SPAD is nearly zero or negative, and ideally all free carriers have been swept out of the depletion region.

The SPAD’s state needs to be restored to the idle state, so the SPAD is sensitive to single charge carriers again. The restoration occurs during the recharge phase. Recharge is achieved by increasing the excess bias across the SPAD back to the desired value. In a passively quenched SPAD, the recharge phase is a simple RC circuit, with the quenching resistance in series to the parasitic capacitance. In practice, however, many passively quenched circuits use a transistor operating as a current source, meaning that the excess bias voltage is better approximated as a linear function during this time. In actively quenched circuits, the recharge behavior will depend on the quenching circuit. In addition, there will be a variation in the parasitic capacitance because the width of charge separation in the p–n junction changes; however, this variation is usually small enough to be neglected.

It might be confusing that the current into the diode is the same sign during an avalanche and recharge phase, since the voltage across the SPAD increases and decreases with the same direction of current. However, different effects are dominating during different phases, so the voltage change cannot be associated with current flowing in a particular direction. During recharge, the current causes a buildup of charge separation to create an unstable system, whereas during an avalanche the current is that unstable system’s release of energy.

During recharge, the SPAD will be initially insensitive to injected carriers, but it will become increasingly sensitive as the excess bias changes. Carriers injected during recharge can be problematic for silicon SPADs. If no carriers cause an avalanche, the recharge stage should be complete and the SPAD will remain idle until another carrier is injected, when all the phases will repeat.

7.2.4 Example Waveforms

This section presents example waveforms from an FEM model of a planar silicon SPAD in a standard quenching circuit, as shown in Figs. 7.2 and 7.3. A 2 ×40 μm2 diode with a breakdown voltage of approximately 19 V was simulated at an excess bias of 3 V. The SPAD was split into 0. 1 ×0. 1 μm2 diodes, making a total of 20 by 400 simulated diodes. The concentration of carriers within each diode was governed by (7.10), (7.7), and (7.11). The constants used were a diffusion coefficient of 17 ×108 μm2 ∕ s, a space-charge resistance-unit area of 12 kΩ μm2, a quenching resistance of 300 kΩ, and a total parasitic capacitance of 300 fF. The parasitic capacitance was assumed to be the sum of 195 fF from the guard ring, 5 fF from the thresholder’s transistor gate, and 100 fF from the diode capacitance. The initial current densities were assumed to be 0 A ∕ μm2 for all element diodes, except for one diode with a current density of 1. 6 ×10 − 6 A ∕ μm2 ∕ s, corresponding to the injection of a single charge carrier. Photon-assisted spreading was ignored, as this diode is a relatively small planar diode that is unlikely to have photon-assisted spreading.
Fig. 7.3

Standard SPAD circuit with a voltage source, SPAD, quenching resistance, capacitors, and inverter is shown. The capacitors represent the parasitic capacitances from the guard ring and transistor gate, and are approximately 10–100 s of fF. The resistor varies from approximately 100 kΩ to 1 MΩ. During simulation, the SPAD is normally replaced by a model shown in Fig. 7.2

The voltage drop across the SPAD is shown in Fig. 7.4 as a function of time. The voltage drop remains relatively small during the buildup phase, with a sizeable increase only during the quench phase of the avalanche. Once the voltage drop is the same value as the excess bias, ionization is assumed to have stopped. This occurs after approximately 1 ns in this diode, while the voltage returns to zero during the recharge phase.
Fig. 7.4

Voltage drop (top) and current density (bottom) vs. time in the various phases of an avalanche in log scale. Avalanches triggered in the center (solid line) and in the edge (dashed line) of the diode are shown. The superimposed lines represent current densities 0, 1, 5, 10, and 15 μm away from initiation, respectively

The current densities for the element diodes, also shown in Fig. 7.4 as a function of time, increase rapidly when the avalanche spreads to that particular region of the diode. The saturated value of current density is limited by the space-charge resistance; once a particular portion of the diode is space-charge limited, the voltage drop across the current source should be the breakdown voltage. Because the element diodes’ capacitances are small compared to the total capacitance, nearly all of the ionization current exits the element diodes. After ionization ceases, a small current will continue to exit the diodes, as the voltage across the diode capacitance must also be recharged. The direction of the current is the same in both cases.

Figure 7.4 presents both an avalanche triggered in the center of the diode and on the edge of the diode. As the diode initially sources less current when it is triggered on the edge, the voltage drop is smaller and the avalanche spreads more quickly. The difference in quenching time in this diode is approximately 200 ps; connecting multiple thresholders and a picosecond-resolution time-to-digital converter (TDC1) to this diode would yield position sensitivity [14]. The current densities as a function of distance are shown during the buildup and quenching/spreading phases in Fig. 7.5. In this particular diode, the buildup phase will last approximately 35 ps, and the avalanche will have spread almost 1. 5 μm in all directions, with space-charge limited current density in a circular area with a radius of approximately 1 μm. The spreading and quenching phase will last around 1 ns.
Fig. 7.5

Current density after triggering: at 5 ps intervals during buildup (left); at 100 ps intervals during spread and quench phases (right). The avalanche is triggered in the center. Due to symmetry, the current density in the junction varies as a function of position to the avalanche initiation triggering position

The spreading speed of the avalanche will slow as the voltage across the quenching resistance increases, as the later current density curves show. After ionization ceases and recharge begins, the current density across the diode will be uniform due to the recharge of the diode capacitance. In reality all of the avalanche phases are based on statistical processes, and the presented, deterministic curves only capture the essence of the expected case. Many factors, including ionization noise, photon-assisted spreading, and environment variations, will change variable governing the ionization and spread. However, this example is useful for the standard operating conditions of many SPADs and establishes a baseline for functionality.

7.2.5 Pulse-Shaping

While many circuit architectures are possible for pulse-shaping, the majority of published work contains a single comparator connected to the SPAD. In CMOS-based circuits, this comparator is often a minimum-sized inverter or a thresholder. The comparator will output a digital-level signal about the state of the SPAD. For a SPAD with a simple resistance for a quenching circuit, the falling edge of the output inverter’s waveform will signal an avalanche’s onset.

While a single sample of the waveform is sufficient for counting single photons and obtaining times-of-arrival, there is additional information in the output waveform that can be obtained. As described earlier, the spread of the avalanche can change the output waveform. For example, if a large-area SPAD receives an enormous number of photons simultaneously, the voltage across the quenching resistance will rise much more quickly than if a single photon was received. In a similar fashion, if a SPAD has a rectangular active area with one side much longer than the other, initial carriers injected at the edge of the major axis can create a slower voltage rise than when injected in the middle. For specialized applications requiring these types of information, circuitry often samples the output waveform multiple times. This is most commonly done with a pair of thresholders with their outputs connected to some sort of TDC.

SPADs that rely on multiple samplings of the output waveform are generally named after their target application. Compensated SPADs are used to compensate for changes in the SPAD’s output waveform for the number of impinging photons [11]. As previously described, when a large number of photons are incident on a large detector in a small time window, the current in the SPAD will increase much more quickly than otherwise. For jitter-sensitive applications, such as 3D imaging, this effect can create time-of-arrival (TOA) differences in the 100 s of picoseconds. Compensated SPADs are a subclass of photon-number-resolving SPADs, which sample the output waveform to gain information about the number of impinging photons [12].

Position-sensitive SPADs have been shown that use the rise time of the waveform to obtain information about the initiation location of the avalanche [13]. There are a number of effects that make these detectors less useful and more difficult to use than one might imagine. The avalanche spread slows as the avalanche quenches, creating different position sensitivity in the diode’s middle than on the edges. In a symmetric diode, only the position from the center may be available. For example, in an elliptical diode with a minor axis that is short compared to the major axis, photons triggered at either edge of the major axis will produce the same output waveform.

7.2.6 Uncorrelated Noise: Dark Counts

Dark counts are a source of intrinsic noise in SPADs, and are generally characterized in terms of the dark count rate (DCR), that is the number of avalanches occurring in a SPAD when there is no light impinging on the active area. DCR sources can be roughly classified into thermal noise, trap-assisted sources, and tunneling-assisted sources, though sources such as trap-assisted tunneling may fall into both categories. A graphical representation of the noise’s relation to the energy bands is shown in Fig. 7.6.
Fig. 7.6

Band diagram of a SPAD junction. Squares represent traps caused by lattice defects. The sources of dark counts are: thermal noise (1), trap-assisted noise (2), afterpulsing (3a and 3b), trap-assisted tunneling (4), tunneling-assisted (5) noise. After [1]

The amount of tunneling-assisted noise is strongly dependent on the doping of the junction and excess bias, and only weakly dependent on the temperature. This type of noise has been shown to be problematic when working with deep submicron CMOS processes, though its effects have been mitigated at the 130 nm node by using existing or modifying doping profiles of implants as appropriate [14]. Whether or not the effects will be severe in SPADs in more advanced CMOS processes remains to be seen, though progress has been made in CMOS processes with a feature size of 90nm [15]. SPADs can be constructed with very little tunneling-assisted noise in older CMOS processes, especially in 0. 35 μm and 0. 8 μm processes [16, 17].

Trap-assisted noise depends strongly on both the CMOS process and the temperature. Traps are lattice defects in silicon that can hold and release carriers. Traps are most prevalent near the surface, and can also be problematic near isolation layers, such as shallow trench isolation (STI). STI-based guard rings can have prohibitive amounts of trap-assisted noise due to their introduction of a trap-laden surface next to the depletion region. For diodes without enormous amounts of tunneling-assisted noise, the trap-assisted noise will limit the noise level above a certain temperature, and below this temperature the tunneling-assisted noise will dominate.

The DCR in SPADs is known to have a long tail; that is, a few noisy pixels source most of the dark counts [2]. Care must be given when examining the median and mean DCR, as the median can hide the poor performance of these noisy pixels. Whether or not a SPAD is “too noisy” depends on the target application and the SPAD construction. Photon-starved applications require lower noise rates. It is nearly impossible to predict DCR in SPADs without prior fabrication. The concentration of traps, for example, can vary significantly from process to process, as it depends on the doping levels and annealing steps in the CMOS process. Some environments, such as radioactive ones, will cause the number of traps to increase over time [18]. However, traps can also be used in the characterization and stabilization of DCR. Overall, noise rates in the single-digit MHz per square millimeter range are quite common for CMOS-based SPADs at room temperature [19]. At a noise rate of 5 MHz per square millimeter, a 10 μm diameter circular SPAD would have an expected DCR that is just under 400 Hz.

7.2.7 Correlated Noise: Afterpulsing and Other Time Uncertainties

There are three main sources of correlated noise: afterpulsing, electronic crosstalk, and optical crosstalk. Additionally, variations in dead time under high photon fluxes is covered in this section, as it causes signal distortion that is correlated with the count rate.


During the later portion of the recharge phase, sufficient excess bias exists such that an injected carrier can cause another avalanche. This is problematic in silicon detectors, as lattice defects can hold carriers after bursts of current and release them on the order of nanoseconds [20]. This unwanted, correlated activity is termed afterpulsing, and can have a significant effect in the first 50 ns or so following an avalanche [21]. The effect is highly temperature dependent, with longer dead times required for the same afterpulsing probability at very cold temperatures [22].

The recharge time thus becomes a trade-off between afterpulsing and detector dead time. If the dead time is set too low, then after-pulsing becomes problematic. If the dead time is set too high, then the detector spends too much time inactive from recharge. The ideal dead time will vary with application, detector size, and temperature. Using a quenching transistor instead of a quenching resistor allows the dead time to be changed through a bias voltage to the transistor’s gate, which is a common technique in CMOS-based SPADs [18].

Optical and Electrical Crosstalk

A large number of free carriers are generated during an avalanche. Some of these carriers will recombine and create additional photons that can cause optical crosstalk. This effect is most significant in large diodes with small separation distances. Large diodes have larger parasitic capacitances, increasing the number of carriers involved in an avalanche that increases the chance of generating a photon by recombination. Smaller separation distances imply that any recombination-generated photon is less likely to be absorbed before impinging on the next SPAD. Optical crosstalk probabilities higher than 20% have been measured in tightly packed SPAD arrays [23]. Some silicon photomultipliers include optical isolation of SPADs to lower this probability [24]. At the other end of the range, a CMOS chip with pixels containing a well-isolated SPAD and logic will have negligible crosstalk, as has been observed [5].

Further reduction of the number of avalanching carriers may be best achieved by reducing the active area of a SPAD, and thus its capacitance at a cost of lower fill factor if the pixel pitch is kept constant. Figure 7.7 shows the impact of a pixel near saturation onto the neighboring pixels at their nominal DCR values, indicating immeasurable crosstalk in the array structure of the design in [16].
Fig. 7.7

Crosstalk measured in a 32 ×32 array of low-pitch passively recharged pixels, when the center pixel is selectively illuminated near saturation with an optical fiber [16]

When multiple p + –n junctions are located in the same n-well, or several p–n + junctions sit on the substrate, the hot carriers exiting the depletion region can bounce around the substrate, eventually being injected into the depletion region of another diode. This effect is electrical crosstalk. Electrical crosstalk has been found to be negligible in CMOS-based arrays when each SPAD is isolated in its own well [5].

Crosstalk can be measured experimentally by observing the correlation between events in two diodes; it is quite difficult to separate observation of optical and electrical crosstalk. To estimate the optical crosstalk probabilities, three things are needed. First, the geometries of the two SPADs under question are required. Second, the photon emission rate per charge carrier must be known, along with the number of carriers involved in the avalanche. Finally, the spectrum of emitted photons must also be known.

Charge Pile-Up

As mentioned earlier, avalanches can occur during the recharge phase, causing distortions in the dead time and also count rate. This effect is commonly called charge pile-up. Pile-up causes a much faster saturation of counts than would be expected. With a dead time of 1 μs, a saturated count rate that is less than 10% of the maximum 1 MHz value has been observed, though the count rate can be linearized to closely match the expected value [14]. The effect will significantly distort the SNR and needs to be considered when the SPAD is operating with a count rate that is a sizeable fraction of the maximum count rate. The statistics of this effect have been studied, with possible compensation.

7.2.8 Sensitivity: Photon Detection Probability

If light creates the avalanche-initiating electron–hole pair, the initial carrier depth is a strong function of the photon’s energy, and hence its wavelength. A photon’s absorption depth in silicon is an exponential process when the photon energy is larger than the band-gap. The large difference in absorption depth in silicon, shown in Fig. 7.8, is caused by silicon’s indirect band-gap. In indirect band-gap materials, phonons must also impart some energy for electron–hole pair generation. This is not the case for direct band-gap materials. The photon detection probability (PDP) analysis for silicon is easily extendable to other materials if the mean absorption depth in that material is known as a function of the incident photon energy.
Fig. 7.8

Mean penetration depth vs. photon wavelength in silicon [53]

Due to the fixed location of the depletion and multiplication regions in most silicon SPADs, there is an ideal mean absorption depth for photons. Light with a mean absorption depth that is too small, such as ultraviolet (UV) light, will create carriers too close to the surface. These carriers will probably recombine before reaching the multiplication region. Light with a large mean absorption depth, such as infrared light, either will create electron–hole pairs too deep in the silicon, or will not create the pairs at all. For planar silicon detectors, the ideal wavelength is usually blue light with a wavelength in the 400–500 nm range. Other materials, such as SiC or InGaAs/InP, shift the optimal wavelength into the UV or infrared.

The PDP can be calculated if the avalanche probability as a function of electron–hole pair creation is known. This section will present such a calculation based on a model derived from [25]. This function will be denoted as p(z). Combining p(z) with the probability of electron–hole pair generation at that depth by a specific wavelength of light will yield the PDP for that specific wavelength. Calculating p(z) in the multiplication region is straightforward in a numerical manner when the ionization coefficients as a function of depth are known. The ionization coefficients of silicon have been experimentally measured as a function of the electric field. The electric field can be calculated if the doping levels are known, and for a well-based SPAD in silicon the doping levels can normally be calculated from the breakdown voltage. Thus, the breakdown voltage, in tandem with assumptions about the diode construction and measured results from the literature, gives sufficient information to calculate the PDP.

Once the ionization coefficients are known, p(z) is calculated as follows for a p + –n SPAD with the same ionization coefficients of electrons and holes, though the extensions to an p–n + SPAD or a SPAD with different electron and hole ionization coefficients is straightforward. Let pe(z) and ph(z) be the respective probabilities that an electron and hole at a depth z trigger an avalanche. For an electron–hole pair, p(z) is the probability that the hole or the electron generate the avalanche, with p(z) = pe(z) + ph(z) − pe(z)ph(z).

The value of p(z) is related to the value of p(z + dz) by the probability that the electron does or does not ionize and generate an electron–hole pair between z and z + dz. If “A” signifies a ionization-generated carrier causing an avalanche and “B” the initial carrier causing an avalanche, then \(\mathrm{P}[\mathrm{avalanche}] = \mathrm{P}[\mathrm{A\ or\ B}] = \mathrm{P}[\mathrm{A}] + \mathrm{P}[\bar{\mathrm{A}}] \cdot \mathrm{P}[\mathrm{B}\vert \bar{\mathrm{A}}]\). The electron will ionize between z and z + dz with probability α(z) ⋅dz, so the probability of an avalanche caused by a generated carrier is P[A] = α(z) ⋅p(z) ⋅dz. Note that the generated carriers are assumed to be created at a depth of z, although if they were created instead at z + dz the difference would vanish. Statement B is independent of A, as ionization will not significantly alter the electric field, thus implying that \(\mathrm{P}[\bar{\mathrm{A}}] \cdot \mathrm{P}[\mathrm{B}\vert \bar{\mathrm{A}}] = (1 - \alpha (z) \cdot p(z) \cdot \mathrm{d}z){p}_{\mathrm{e}}(z + \mathrm{d}z)\). Thus, the equation relating pe(z) to pe(z + dz) is:
$${p}_{\mathrm{e}}(z) = \alpha (z) \cdot p(z) \cdot \mathrm{d}z + (1 - \alpha (z) \cdot p(z) \cdot \mathrm{d}z){p}_{\mathrm{e}}(z + \mathrm{d}z).$$
A differential equation for dpe(z) ∕ dz can be found by rearranging the terms above and taking the limit as dz goes to zero, as
$$\frac{\mathrm{d}{p}_{\mathrm{e}}(z)} {\mathrm{d}z} = \alpha (z) \cdot p(z) \cdot ({p}_{\mathrm{e}}(z) - 1).$$
Similarly, for holes
$$\frac{\mathrm{d}{p}_{\mathrm{h}}(z)} {\mathrm{d}z} = -\alpha (z) \cdot p(z) \cdot ({p}_{\mathrm{h}}(z) - 1).$$
Assuming the depletion region starts at z0 in the p + -doped side and ends at z1 in the n-doped side, the boundary conditions to the solution of (7.13) and (7.14) are ph(z0) = 0 and pe(z1) = 0. To estimate the equations’ solutions, pe(z1) = 0 can be swept from 0 to 1, with numerical analysis yielding pe(z), ph(z), and p(z) for z between z0 and z1. For the initial value of pe(z), which gives pe(z1) = 0, the boundary conditions will be met and values for all p functions will be known between z0 and z1.

If the electron–hole pair is generated outside of the depletion region, then the triggering probability will vary depending on the generation location. For example, carriers generated in the well will increase the PDP, but at the expense of distortions in the timing jitter [18]. In this instance, it will be assumed that p(z) varies linearly between 0 at the surface and p(z0), and that p(z) is 0 everywhere else. There is an additional effect that merits mention. There is material between the air and the surface of the SPAD, commonly called the optical stack. Materials such as silicon dioxide do not have uniform transmittance curves, and extremely accurate PDP calculations should include the effects of the optical stack.

Finally, since the triggering probability as a function of electron–hole pair generation depth is known, and the probability density function of pair generation at that depth is known for any particular wavelength, the PDP at a particular wavelength is the integral of the product of the triggering probability function with the PDF for that particular wavelength. Theoretical PDP curves are shown in Fig. 7.9 for a p + –n junction at a depth of 200 nm with a breakdown voltage of approximately 18.9 V. Ionization coefficients are taken from [26].
Fig. 7.9

Modeled photon detection probability vs. applied voltage for impinging light with a wavelength of 425 nm (left) and vs. wavelength at an excess bias voltage of 3 V (right)

7.2.9 Wavelength Discrimination

When the depth of a SPAD’s junction is increased, sensitivity to blue light will decrease more quickly than sensitivity to red light. This technique can be used for wavelength discrimination between junctions at different depths, and SPADs with different junction characteristics on a single chip have been realized [27]. In addition, modulating the excess bias will change the avalanche probability as a function of electron–hole generation depth, and allow some portion of wavelength information to be extracted from a single junction [28]. However, the first method is strongly dependent on the CMOS process having the correct layers for two different types of SPADs, and it can only discriminate a small number of wavelengths, while the second technique is not very sensitive due to the small fluctuations in PDP ratio. Of course coupling with optical filters or prisms can create wavelength sensitivity in a particular system that utilizes SPADs. Optical pass-band filters are especially common in 3D imaging, as they allow the rejection of background light.

7.3 Fabricating Monolithic SPADs

7.3.1 Vertical Versus Planar SPADs

There exist two main implementation styles for both APDs and SPADs. In the first style, known as reach-through APD (RAPD), one builds a \(\mathrm{p} + \mbox{ \textendash }\pi \mbox{ \textendash }\mathrm{p}\mbox{ \textendash }\mathrm{n}\) structure [3]. When reverse biased, the depletion region extends from the cathode to the anode. Thus, the multiplication region is deep in the p ∕ n + junction. Due to the depth of the multiplication region, this device is indicated for absorption of red and NIR photons up 1. 1 μm (for silicon). Since the photoelectrons drift until they reach the multiplication region, a larger timing uncertainty is generally observed.

The second known implementation style is compatible with planar CMOS processes, and it involves shallow or medium depth p or n layers to form high-voltage pn junctions. Cova and others have investigated devices designed in this style since the 1970s, yielding a number of structures [2]. All these structures have in common a p–n junction and a zone designed to prevent premature edge breakdown (PEB). An example of the early structures is shown in Fig. 7.10. In [31], n +  ∕ p + enrichment in p-substrate was used, while PEB was prevented by confining p + enrichment to the center of the APD.
Fig. 7.10

Cross-section of an early planar SPAD

More recently, many authors have developed devices using dedicated planar and nonplanar processes, achieving superior performance in terms of sensitivity and noise. A good example is the work of Kindt [32]. The main disadvantage of using dedicated processes is generally the lack of libraries that can support complex functionalities and deep-submicron feature sizes, thus limiting array sizes. An interesting alternative is the use of a hybrid approach whereby the APD array and ancillary electronics are implemented in two different processes, each optimized for performance and speed, respectively [33]. If the ancillary electronics is implemented in CMOS, high degrees of miniaturization are possible. The price to pay is increased fabrication complexity.

7.3.2 Implementation in Planar Processes

Premature Edge Breakdown

Implementing a SPAD in a planar process first involves finding a way to prevent PEB. PEB consists of spurious, preferential avalanching on the periphery of the SPAD active area, thus causing a drastic reduction of sensitivity. Several techniques exist to implement PEB prevention. In essence, the techniques have in common the reduction of the electric field at the edges and/or the increase of the breakdown voltage locally, so as to maximize the probability that the avalanche is initiated in the center of the multiplication region. This is the region where the critical electric field for impact ionization is reached and, possibly, exceeded.

In Fig. 7.11, four of the most used structures are shown. In (a), the n + layer maximizes the electric field in the middle of the diode. In (b), the lightly doped p − implant reduces the electric field at the edge of the p + implant. In (c), a floating p implant locally increases the breakdown voltage. With a polysilicon gate, one can further extend the depletion region (gray line in the figure). Finally, in a process with trenches it is possible to decrease the electric field using the geometry of solution (d). When trenches are used, one needs to adopt techniques to prevent traps accumulated in the trench during fabrication from inducing PEB. An effective technique proposed in [16] consists of using several layers of doped semiconductor material with decreasing doping levels from the trench to the multiplication region. The purpose is to achieve short mean-free paths close to the trench, thereby forcing carriers generated there to recombine before reaching the multiplication region.
Fig. 7.11

Premature edge breakdown prevention mechanisms in planar and semiplanar processes

The structures of Fig. 7.11(a)–(c) are indicated in a number of CMOS technologies, while a trench-based structure (d) is mostly appropriate in deep-submicron CMOS technologies, where deep and medium tubs are not available without a major change in the fabrication process. In the remainder of the chapter, we focus our attention on schemes (b) and (d) because they require, in general no modifications to the process and thus enable the design of large SPAD array chips in standard CMOS technologies.

Quenching and Recharge Implementation

Upon design of a p–n junction capable of withstanding relatively high voltages and whereby PEB is practically prevented, the device may be biased above breakdown into Geiger mode. As discussed earlier, in this mode of operation the avalanche must be quenched to prevent destruction of the device. There exist a variety of avalanche quenching techniques, active and passive, that perform this task. In active methods, the avalanche is detected, generally using a thresholder as described earlier, and stopped by acting on the bias. In passive methods, the p–n junction bias is self-adjusted, for example, by a ballast resistor. Recharge can also be active and passive. In active recharge, the bias across the diode is reestablished by a switch activated by an avalanche detector. In passive recharge, the ballast resistor performs this task.

Figure 7.12 shows the cross-section of a SPAD and simple circuitry to perform passive quenching and recharging. Upon photon detection, buildup and spread force a current through the device and the ballast resistor; this in turn develops a voltage drop that significantly raises voltage V (t). Upon quenching, recharge begins bringing the device back to the idle state. This process generates a current pulse that is converted to a digital voltage level by means of a pulse shaping circuitry, also shown in the figure. The pulse shaper is also acting as an impedance adapter to drive the load of the column readout often employed in a SPAD matrix.
Fig. 7.12

SPAD cross-section in a conventional CMOS process (left); passive quench and recharge circuitries, as well as pulse shaping (right)

The ballast device may be implemented as a resistor or as an active element acting as a nonlinear resistor (Mq in Fig. 7.12). Assuming that the latter can be approximated as a linear element, recharge voltage V (t) yields:
$$V (t) \approx {V }_{\mathrm{E}}{\mathrm{e}}^{-\frac{t-{t}_{0}} {\mathit{RC}} },\ t \geq {t}_{0},$$
where R and C are estimated overall resistance and capacitance to the ground at the cathode, and VE is the excess bias voltage, that is the voltage above breakdown at which the SPAD is biased. Time t0 is the instant at which the quenching is complete. Upon proper selection of the bias (the signal BIAS in Fig. 7.12), Mq may also be operated in active mode, thus causing a controlled recharge. When controlled recharge is applied, V (t) becomes:
$$V (t) \approx {V }_{\mathrm{E}} -\frac{{I}_{\mathrm{R}}} {C} (t - {t}_{0}),\ {t}_{0} \leq t \leq {t}_{0} + \frac{{\mathit{CV }}_{\mathrm{E}}} {{I}_{\mathrm{R}}},$$
where IR is the current discharged by Mq of Fig. 7.12. In reality, the transistor may not be operated in strong inversion throughout the recharge, and thus (7.16) is only an approximation. The accuracy of this approximation is discussed in the literature.
The advantage of using an active recharge is a better control of the detection cycle and in particular of the overall time spent during quenching and recharge, known collectively as dead time. Furthermore, active recharge can also be performed in multislope mode to allow for a precise control of dead time over larger SPAD arrays, thus improving overall detection uniformity, especially in high illumination regimes. Figure 7.13 shows three typical recharge profiles. Passive recharge is the most commonly used technique, while active recharge is used in many devices whereby the recharge process has to respond to specific requirements. Figure 7.13 also shows two types of active recharge known as single- and double-slope active recharge. Single-slope recharge is simple to implement requiring only one bias per SPAD. In double-slope recharge [34], the SPAD’s dead time is effectively controlled by time tR at which the second slope is activated. If the voltage VR achieved at this point still disables the avalanche, then it is guaranteed that the device is still in dead time regime. Thus, the dead time can be triggered by one properly timed control signal, and thus it is independent of R.
Fig. 7.13

SPAD recharge mechanisms: passive (left), single-slope active (right), and double-slope active (center)

Dead time is an important parameter, as it determines the maximum count rate of a detector and thus the saturation intensity. A variety of active quenching and recharge circuits can be found in the literature whereby the differentiating factors are complexity as well as dead time programmability and stability. One of the most important considerations in the selection of the best possible recharge mechanism is simplicity, which is of particular importance when it comes to miniaturization.

7.3.3 SPAD Nonidealities

Individual SPADs are characterized by a number of performance measures discussed earlier. In this section, these measures are summarized in terms of sensitivity, measured as PDP, noise performance, measured a rate of spurious pulses due to thermal events or DCR. Other parameters include timing jitter, also known somewhat inappropriately as timing resolution, afterpulsing probability, and, as mentioned earlier, dead time. These parameters have appeared in the literature for individual SPADs implemented in a variety of CMOS processes [48, 15, 16, 17, 19, 33, 34, 35, 36, 37, 38, 39]. Some performance parameters found in individual SPADs are described in Table 7.1 for four different implementations in CMOS submicron and deep-submicron processes achieved by the researchers of our group.
Table 7.1

Comparison of CMOS SPAD performance for a variety of published devices


0. 8 μm [17]

0. 35 μm [20]

130 nm [16]

130 nm [42]


Timing jitter (@ 637 nm)






DCR (@ 300 K)

350 (VE: 5.0 V)

750 (VE: 3.3 V)

220 (VE: 2.0 V)

1,221 (VE: 0.6 V)


Active area






Mean DCR per active area





Hz ∕ μm2

Breakdown (VBD)






Dead time

 < 40





PDP @ 460 nm

26 (VE: 5.0 V)

40 (VE: 3.3 V)

26 (VE: 2.0 V)

17.5 (VE: 0.6 V)


EM spectrum (PDP > 1%)











aRecently improved measurement

As mentioned earlier, the physical process underlying afterpulsing has been thoroughly researched in the literature. More details on afterpulsing characterization can be found in [16, 21, 43] for the devices described in this work.

7.3.4 SPAD Array Nonidealities

When implemented in an array, other performance measures become relevant to the quality of the imager. Besides dead time uniformity, timing jitter uniformity and PDP uniformity, as well as DCR uniformity and crosstalk have to be accounted for and properly characterized. Figure 7.14 shows the dead time and PDP uniformities achieved in a 32 ×32 pixel array implemented in a 0. 8 μm CMOS process [17].
Fig. 7.14

PDP (left) and dead time uniformity (right) in a 32 ×32 array of low-pitch passively recharged pixels [17]

PDP of course will also be a function of the input wavelength as derived in the earlier sections. Due to the band-gap of silicon, in CMOS SPAD implementations, the sensitivity range is mostly in the visible spectrum, with somewhat reduced near infrared and near UV PDP.

Figure 7.15 shows a plot of PDP as a function of wavelength for various values of excess bias voltage VE for an implementation of SPADs in 130 nm [16].
Fig. 7.15

PDP in a SPAD implemented in 130 nm CMOS process as a function of wavelength and excess bias [16]

Figure 7.16 shows the timing jitter on a SPAD implemented in 0. 35 μm CMOS technology. In the inset of the figure, the uniformity of such jitter can be seen in an array of pixels integrated on the same chip measured by exposing the chip to a cone of light from a pulsed laser source. In this case, a femtosecond Ti:Sapphire laser source doubled to achieve a wavelength 488 nm was used. The uniformity in time is also very important, especially in photon-starved applications whereby long measurements may be needed to reach good accuracy.
Fig. 7.16

Timing jitter performance reported in [36]. The inset shows the FWHM timing jitter over a 2 mm sized array of SPADs

Crosstalk issues were discussed earlier and a plot of measured crosstalk in a monolithic SPAD array implemented in 0. 8 μm CMOS process is shown in Fig. 7.7. Afterpulsing is well reported in the literature. Afterpulsing in submicron CMOS SPADs is characterized in detail [20, 36]. The variation of afterpulsing across a large array is generally contained due to the lithographically well-matched geometries that ensure well-matched capacitances among SPAD pixels and thus a tight control on the number of charges involved in avalanches.

7.4 Architecting SPAD Arrays

7.4.1 Basic Architectures

SPADs are dynamic devices generating a digital pulse upon detection of a photon. Unlike conventional diodes, they cannot hold a charge proportional to the overall photon count. Photopulses must be counted in situ or read outside the image sensor and counted externally. Due to their reaction speed and low timing uncertainty, SPADs are most appropriate for photon TOA evaluation. However, even this operation must be performed upon photon detection. To address this problem, researchers have adopted a number of architectures that take advantage of the low propagation delay or high level of miniaturization achievable in standard submicron and deep-submicron CMOS technologies.

The currently available architectures are differentiated based, respectively, on processing and readout mechanisms: (1) on-chip, whereby processing is shared among all pixels and random-access or sequential readout is used; (2) in-column, whereby processing is shared among clusters of pixels, for example, columns, through event-driven mechanisms, and cluster-based readout is used; (3) in-pixel, whereby processing is pixel-specific and the result is saved locally; parallel or random-access readout is subsequently performed.

When any kind of sharing is used, trade-offs between pixel utilization, column/cluster size, and detection bandwidth are generally the result. In these cases, understanding application specifications is key to an appropriate use of the available techniques. We present a few examples hereafter as exemplifications of various architectures.

7.4.2 On-Chip Architecture

An example of an on-chip architecture is the design proposed in [17]; it comprises a matrix of 32 ×32 pixels, each with an independent SPAD, a quenching mechanism, pulse shaping, and column access circuitry. The readout scheme was based on random access whereby all time-sensitive operations had to be performed off-chip, and an overall jitter as low as 70 ps was measured on a pixel while the entire array was operating. An IRF of 79 ps was measured in [44]. The block diagram of the imager and the pixel schematic are shown in Fig. 7.17. The micrograph of the chip is shown in Fig. 7.18.
Fig. 7.18

32 ×32 SPAD array with random access readout. The chip was implemented in 0. 8 μm CMOS technology

Fig. 7.17

Block diagram and pixel schematic of the 32 ×32 SPAD array with random access readout

7.4.3 In-Column Architecture

Among in-column architectures, at least two variants were devised to address the readout bottleneck. The first, known as event-driven variant, consists of using the column as a bus that is addressed every time a photon is detected. The address of the row where the photon was detected is sent to the bottom of the column where the TOA is evaluated, either off chip [21, 36] or on chip [19, 45]. The second approach, known as latchless pipeline [46], uses the column as a timing-preserving delay line. Every photon triggers a pulse that is injected onto the pipeline at a precise location that corresponds to the physical place where the pixel is situated. The row information is thus encoded in the timing of the pulse arrival at the end of the pipeline, thus it can be sequentially reconstructed by a single TDC at the bottom of the column. The TDC will also detect the exact TOA of the photon within a predefined window of time.

Figure 7.19 shows a schematic of the injection mechanism at each pixel. The avalanche current is sensed and converted into a digital voltage pulse, as before, by a properly designed inverter. The L to H transition at the inverter’s output pulls down node “X” through transistor TPD and resistor RPU, provided that gating transistor TG is enabled by signal “GATE.” The anode of the diode is intentionally set to a negative voltage, as before. Tq was sized for a dead time τDT of 40 ns and by choosing a gating window τG that satisfies inequality τG < τD < τDT. When there is no activity on the preceding delay line, signal “VINj” is at logic level L; hence, the gate of source-degenerated transistor TPP is L, thus the impedance at node “X” is dominated by the impedance at the drain of TPP. When a photon is detected, a pulse is originated at this point and it is propagated toward the remainder of the delay line. When there is activity on the delay line, a logic transition L to H on “VINj” occurs, thus causing “X” to become a low impedance node. During this time, any photon detection in this stage will have no effect on traveling pulses but it will inject spurious pulses onto the line when it is at logic level L, hence the need for gated SPAD operation. To avoid ghost pulses, an appropriately sized NMOS was added to the cathode of the diode. A simplified timing diagram to operate the eight-stage delay line is shown in the inset of the figure. Controls “BIAS” (transistor TB) and “TUNE” are used for coarse- and fine-tuning of the delay line, respectively. The goal is to compensate for technological variations and temperature.
Fig. 7.19

Schematic diagram of the latchless pipelined readout

A chip implementing the concept for a 128 ×2 SPAD array is shown in Fig. 7.20; the architecture was implemented in 0. 35 μm CMOS. The chip also includes a single SPAD line for 8-bit time-uncorrelated photon counting.
Fig. 7.20

Integrated version of the latchless pipeline implemented in 0. 35 μm CMOS technology [46]

7.4.4 In-Pixel Architecture

To the best of our knowledge, the first CMOS designs implementing massively parallel in-pixel single-photon processing were RADHARD2 [21] and SPSD [34]. RADHARD2 comprises a matrix of 32 ×32 pixels, each equipped with an independent counter. The content of the counters is read out in rolling shutter mode at very high speed, thus use of the chip in moderate time-resolution imaging, such as fluorescence correlated spectroscopy (FCS), is possible on a much larger pixel scale than earlier attempts [47].

In this design, the avalanche voltage is sensed by M2 that forces the latch to logic level “1.” Transistor M7 acts as pull-down of the column line that is kept high by resistor RPU, while M6 is the row selection switch, controlled by “RowSEL.” When the column is pulled down, a buffer (not shown in the schematic) controls a pad and the output of the chip for that column is interpreted as a photon detected in the previous interval of time. Transistors M4 and M5 are controlled, respectively, by column line (“ColSET”) and row line (“RowSET”) to force the static memory of a specific pixel to logic level “1,” irrespective of the SPAD state, for testing purposes. M8 is used to operate a global or row-based reset via signal “gRESET,” whereas M3 prevents memory conflicts in case of a SPAD firing during reset. SPAD quenching and recharge are performed by transistor M1 that can be adjusted globally via signal “BIAS,” so as to select a proper trade-off between dead time and afterpulsing probability. The pixel comprises ten NMOS and only two PMOS transistors, thus enabling minimization of the NWELL surface, hence ensuring a pitch of 30 μm (Fig. 7.21).
Fig. 7.21

Schematic diagram of the RADHARD2 pixel with an embedded counter. The content of the counter is read out using a simple pull-down transistor, and it may be set and reset using appropriate controls

The chip micrograph is shown in Fig. 7.22. The inset also shows a detail of the pixels and their column data readout interconnect and row-wise control lines. To construct images with multibit gray levels, a high-frequency readout was put in place capable of reading an entire 1-bit frame in 2. 88 μs [21].
Fig. 7.22

Photomicrograph of RADHARD2, a 32 ×32 parallel-counting pixel array implemented in 0. 35 μm CMOS technology. The inset shows a zoom of 4 ×4 pixels [21]

7.5 Trends in Monolithic Array Designs

More recently, with the implementation of the first SPADs in 130 nm CMOS technologies [37, 42] and 90 nm [48], it has been possible to integrate more functionality on pixel. The pixels of the array in the MEGAFRAME project for example comprise a multibit counter and a picosecond resolution TDC [49, 51] or time-to-amplitude converter (TAC) [50]. One of the early implementations of the MEGAFRAME concept comprises an array of 32 ×32 pixels each of which is capable of performing TOA measurements with picosecond resolution and digital photon counting; it was conceived to operate both in time-correlated single-photon counting (TCSPC) and in time-uncorrelated photon counting (TUPC) modes. Figure 7.23 shows a photomicrograph of the chip.
Fig. 7.23

Photomicrograph of MEGAFRAME, a 32 ×32 pixel array, capable of performing one million TOA evaluations per pixel per second at 119 ps time resolution

The MEGAFRAME potential has been demonstrated in a number of applications involving time-resolved imaging, such as fluorescence lifetime imaging microscopy (FLIM) [49, 50, 51], operating in TCSPC mode, thanks to its high timing resolution and readout speed. TUPC has also shown to be effective in FCS applications, whereas other chips, such as RADHARD2, have been employed successfully [52].

More recently, the MEGAFRAME project has evolved toward higher lateral and time resolutions with the design of a new sensor comprising 160  × 128 pixels capable of 55 ps time resolution [52, 53]. The design includes a phase-lock loop stabilized 10-bit TDC array with an IRF of 140 ps (FWHM).

7.6 Conclusions

In this chapter, we have introduced the fundamental mechanisms at the basis of monolithic SPADs with a particular focus on devices implemented in a planar CMOS process. We have outlined the challenges of implementing SPADs in deep-submicron CMOS technologies. Finally, we have covered the issues related to large SPAD arrays and the development of high-performance devices.


  1. 1.

    A TDC is a sort of chronometer capable of discerning pulse position with high precision.



The authors are grateful to current and former graduate students and postdoctoral fellows of the AQUA group and the MEGAFRAME project that made this research possible. Special thanks go to Lucio Carrara, Marek Gersbach, Cristiano Niclass, and Maximilian Sergio who were responsible for the designs outlined here, as well as Fausto Borghetti, Claudio Favi, Robert Henderson, Mohammad Karami, Theo Kluter, Estelle Labonne, Yuki Maruyama, Justin Richardson, David Stoppa, and Richard Walker who codesigned the chips. The authors acknowledge Giordano Beretta, Claudio Bruschini, Dmitri Boiko, Neil Gunther, Lindsay Grant, David Li, and Luciano Sbaiz for useful discussions.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  1. 1.Technical University DelftDelftThe Netherlands

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