Advertisement

Green Secure Processors: Towards Power-Efficient Secure Processor Design

  • Siddhartha Chhabra
  • Yan Solihin
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6340)

Abstract

With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.

Keywords

Power Analysis Secure Processor Architectures Memory Encryption Memory Authentication Embedded Systems Security 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Huang, A.: Hacking the Xbox: An Introduction to Reverse Engineering. No Starch Press, San Francisco (2003)Google Scholar
  2. 2.
    Kumar, A.: Discovering Passwords in Memory (2004), http://www.infosec-writers.com/text_resources/
  3. 3.
    Gassend, B., Suh, G., Clarke, D., Dijk, M., Devadas, S.: Caches and Hash Trees for Efficient Memory Integrity Verification. In: Proc. of the 9th International Symposium on High Performance Computer Architecture, HPCA-9 (2003)Google Scholar
  4. 4.
    Gilmont, T., Legat, J.D., Quisquater, J.J.: Enhancing the Security in the Memory Management Unit. In: Proc. of the 25th EuroMicro Conference (1999)Google Scholar
  5. 5.
    Lie, D., Mitchell, J., Thekkath, C., Horowitz, M.: Specifying and Verifying Hardware for Tamper-Resistant Software. In: IEEE Symposium on Security and Privacy (2003)Google Scholar
  6. 6.
    Lie, D., Thekkath, C., Mitchell, M., Lincoln, P., Boneh, D., MItchell, J., Horowitz, M.: Architectural Support for Copy and Tamper Resistant Software. In: Proc. of the 9th International Conference on Architectural Support for Programming Languages and Operating Systems (2000)Google Scholar
  7. 7.
    Rogers, B., Solihin, Y., Prvulovic, M.: Efficient data protection for distributed shared memory multiprocessors. In: International Conference on Parallel Architectures and Compilation Techniques (2006)Google Scholar
  8. 8.
    Shi, W., Lee, H.H.: Authentication Control Point and Its Implications for Secure Processor Design. In: Proc. of the 39th Annual International Symposium on Microarchitecture (2006)Google Scholar
  9. 9.
    Shi, W., Lee, H.H., Ghosh, M., Lu, C.: Architectural Support for High Speed Protection of Memory Integrity and Confidentiality in Multiprocessor Systems. In: Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, pp. 123–134 (September 2004)Google Scholar
  10. 10.
    Shi, W., Lee, H.H., Ghosh, M., Lu, C., Boldyreva, A.: High Efficiency Counter Mode Security Architecture via Prediction and Precomputation. In: Proceedings of the 32nd International Symposium on Computer Architecture (June 2005)Google Scholar
  11. 11.
    Shi, W., Lee, H.H., Lu, C., Ghosh, M.: Towards the Issues in Architectural Support for Protection of Software Execution. In: Proceedings of the Workshop on Architectureal Support for Security and Anti-virus, pp. 1–10 (October 2004)Google Scholar
  12. 12.
    Suh, G., Clarke, D., Gassend, B., van Dijk, M., Devadas, S.: Efficient Memory Integrity Verification and Encryption for Secure Processor. In: Proc. of the 36th Annual International Symposium on Microarchitecture (2003)Google Scholar
  13. 13.
    Yan, C., Rogers, B., Englender, D., Solihin, Y., Prvulovic, M.: Improving cost, performance, and security of memory encryption and authentication. In: Proc. of the International Symposium on Computer Architecture (2006)Google Scholar
  14. 14.
    Yang, J., Zhang, Y., Gao, L.: Fast Secure Processor for Inhibiting Software Piracy and Tampering. In: Proc. of the 36th Annual International Symposium on Microarchitecture (2003)Google Scholar
  15. 15.
    Zhang, Y., Gao, L., Yang, J., Zhang, X., Gupta, R.: SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors. In: International Symposium on High-Performance Computer Architecture (February 2005)Google Scholar
  16. 16.
    Chhabra, S., Rogers, B., Solihin, Y., Prvulovic, M.: Making secure processors os- and performance-friendly. ACM Transactions on Architecture and Code Optimization 5(4), 1–35 (2009)CrossRefGoogle Scholar
  17. 17.
    Chhabra, S., Rogers, B., Solihin, Y.: SHIELDSTRAP: Making Secure Processors Truly Secure. In: ICCD (2009)Google Scholar
  18. 18.
    NIST: Cryptographic hash algorithm competition (2008), http://csrc.nist.gov/groups/ST/hash/sha-3/index.html
  19. 19.
    Stajano, F., Anderson, R.: The resurrecting duckling: Security issues for ubiquitous computing (supplement to computer magazine). Computer 35, 22–26 (2002)CrossRefGoogle Scholar
  20. 20.
    Rogers, B., Chhabra, S., Solihin, Y., Prvulovic, M.: Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly. In: Proc. of the 36th Annual International Symposium on Microarchitecture (2007)Google Scholar
  21. 21.
    Renau, J., et al.: SESC (2004), http://sesc.sourceforge.net
  22. 22.
    Brooks, D., Tiwari, V., Martonosi, M.: Wattch: a framework for architectural-level power analysis and optimizations. In: Proceedings of the 27th Annual International Symposium on Computer Architecture, ISCA 2000, pp. 83–94. ACM, New York (2000)CrossRefGoogle Scholar
  23. 23.
    FIPS Publication 197: Specification for the Advanced Encryption Standard (AES). National Institute of Standards and Technology, Federal Information Processing Standards (2001)Google Scholar
  24. 24.
    Kgil, T., Falk, L., Mudge, T.: ChipLock: Support for Secure Microarchitectures. In: Proceedings of the Workshop on Architectural Support for Security and Anti-Virus (WASSA) (October 2004)Google Scholar
  25. 25.
  26. 26.
    Standard Performance Evaluation Corporation (2004), http://www.spec.org
  27. 27.
  28. 28.
    Barroso, L.A., Gharachorloo, K., McNamara, R., Nowatzyk, A., Qadeer, S., Sano, B., Smith, S., Stets, R., Verghese, B.: Piranha: A scalable architecture based on single-chip multiprocessing. In: Proc. of the 27th International Symposium on Computer Architecture, pp. 282–293. ACM, New York (2000)Google Scholar
  29. 29.
    Mowry, T.C., Lam, M.S., Gupta, A.: Design and Evaluation of a Compiler Algorithm for Prefetching. In: 5th Intl. Conf. on Architectural Support for Programming Languages and Operating Systems (1992)Google Scholar
  30. 30.
    Sinharoy, B., Kalla, R.N., Tendler, J.M., Eickemeyer, R.J., Joyner, J.B.: Power5 system microarchitecture. IBM Journal of Research and Development 49(4/5), 505–521 (2005)CrossRefGoogle Scholar
  31. 31.
  32. 32.
    Quicklogic: Display Power Optimizer (2008), http://www.quicklogic.com/display-power-optimizer-dpo-overview/

Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Siddhartha Chhabra
    • 1
  • Yan Solihin
    • 1
  1. 1.Dept. of Electrical and Computer EngineeringNorth Carolina State UniversityRaleighUSA

Personalised recommendations