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A Compressive Sensing Algorithm for Many-Core Architectures

  • A. Borghi
  • J. Darbon
  • S. Peyronnet
  • T. F. Chan
  • S. Osher
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6454)

Abstract

This paper describes a parallel algorithm for solving the l 1-compressive sensing problem. Its design takes advantage of shared memory, vectorized, parallel and many-core microprocessors such as Graphics Processing Units (GPUs) and standard vectorized multi-core processors (e.g. quad-core CPUs). Experiments are conducted on these architectures, showing evidence of the efficiency of our approach.

Keywords

Graphic Processing Unit Discrete Cosine Transform Compressive Sensing Sparse Signal Cache Memory 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • A. Borghi
    • 1
  • J. Darbon
    • 2
  • S. Peyronnet
    • 1
  • T. F. Chan
    • 3
  • S. Osher
    • 4
  1. 1.LRI, INRIAUniversité Paris SudOrsayFrance
  2. 2.CMLA, ENS Cachan, CNRSPRES UniverSudFrance
  3. 3.Science and TechnologyHong Kong UniversityHong Kong
  4. 4.Mathematics DepartmentUCLAUSA

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