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Fast Parallel Model Estimation on the Cell Broadband Engine

  • Ali Khalili
  • Amir Fijany
  • Fouzhan Hosseini
  • Saeed Safari
  • Jean-Guy Fontaine
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6454)

Abstract

In this paper, we present fast parallel implementations of the RANSAC algorithm on the Cell processor, a multicore SIMD architecture. We present our developed strategies for efficient parallel implementation of the RANSAC algorithm by exploiting the specific features of the Cell processor. We also discuss our new method for model generation to increase the efficiency of calculation of the Homography transformation by RANSAC. In fact, by using this new method and change of algorithm, we have been able to increase the overall performance by a factor of almost 3. We also discuss in details our approaches for further increasing the efficiency by a careful vectorization of the computation as well as by reducing the communication overhead by overlapping computation and communication. The results of our practical implementations clearly demonstrate that a very high sustained computational performance (in terms of sustained GFLOPS) can be achieved with a minimum of communication overhead, resulting in a capability of real-time generation and evaluation of a very large number of models. With a date set of size 2048 data and a number of 256 models, we have achieved the performance of over 80 sustained GFLOPS. Since the peak computing power of our target architecture is 179 GFLOPS, this represents a sustained performance of about 44% of the peak power, indicating the efficiency of our algorithms and implementations. Our results clearly demonstrate the advantages of parallel implementation of RANSAC on MIMD-SIMD architectures such as Cell processor. They also prove that, by using such a parallel implementation over the sequential one, a problem with a fixed number of iterations (hypothetical models) can be solved much faster leading to a potentially better accuracy of the model.

Keywords

Parallel Implementation Global Memory Hypothetical Model Loop Unroll Cell Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Ali Khalili
    • 1
  • Amir Fijany
    • 1
  • Fouzhan Hosseini
    • 1
  • Saeed Safari
    • 1
    • 2
  • Jean-Guy Fontaine
    • 1
  1. 1.Italian Institute of TechnologyGenovaItaly
  2. 2.School of Electrical and Computer EngineeringUniversity of TehranTehranIran

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