Geometric Algorithms for Private-Cache Chip Multiprocessors

(Extended Abstract)
  • Deepak Ajwani
  • Nodari Sitchinava
  • Norbert Zeh
Conference paper

DOI: 10.1007/978-3-642-15781-3_7

Part of the Lecture Notes in Computer Science book series (LNCS, volume 6347)
Cite this paper as:
Ajwani D., Sitchinava N., Zeh N. (2010) Geometric Algorithms for Private-Cache Chip Multiprocessors. In: de Berg M., Meyer U. (eds) Algorithms – ESA 2010. ESA 2010. Lecture Notes in Computer Science, vol 6347. Springer, Berlin, Heidelberg

Abstract

We study techniques for obtaining efficient algorithms for geometric problems on private-cache chip multiprocessors. We show how to obtain optimal algorithms for interval stabbing counting, 1-D range counting, weighted 2-D dominance counting, and for computing 3-D maxima, 2-D lower envelopes, and 2-D convex hulls. These results are obtained by analyzing adaptations of either the PEM merge sort algorithm or PRAM algorithms. For the second group of problems—orthogonal line segment intersection reporting, batched range reporting, and related problems—more effort is required. What distinguishes these problems from the ones in the previous group is the variable output size, which requires I/O-efficient load balancing strategies based on the contribution of the individual input elements to the output size. To obtain nearly optimal algorithms for these problems, we introduce a parallel distribution sweeping technique inspired by its sequential counterpart.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Deepak Ajwani
    • 1
  • Nodari Sitchinava
    • 1
  • Norbert Zeh
    • 2
  1. 1.MADALGO, Department of Computer ScienceUniversity of AarhusDenmark
  2. 2.Faculty of Computer ScienceDalhousie UniversityHalifaxCanada

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