A Scalable Lock-Free Universal Construction with Best Effort Transactional Hardware

  • Francois Carouge
  • Michael Spear
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6343)

Abstract

The imminent arrival of best-effort transactional hardware has spurred new interest in the construction of nonblocking data structures, such as those that require atomic updates to k words of memory (for some small value of k). Since transactional memory itself (TM) was originally proposed as a universal construction for crafting scalable lock-free data structures, we explore the possibility of using this emerging transactional hardware to implement a scalable, unbounded transactional memory that is simultaneously nonblocking and compatible with strong language-level semantics. Our results show that it is possible to use this new hardware to build nonblocking TM systems that perform as well as their blocking counterparts. We also find that while the construction of a lock-free TM is possible, correctness arguments are complicated by the many caveats and corner cases that are built into current transactional hardware proposals.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Bobba, J., Moore, K., Volos, H., Yen, L., Hill, M., Swift, M., Wood, D.: Performance Pathologies in Hardware Transactional Memory. In: Proc. of the 34th Intl. Symp. on Computer Architecture, San Diego, CA (June 2007)Google Scholar
  2. 2.
    Christie, D., Chung, J.W., Diestelhorst, S., Hohmuth, M., Pohlack, M., Fetzer, C., Nowack, M., Riegel, T., Felber, P., Marlier, P., Riviere, E.: Evaluation of AMD’s Advanced Synchronization Facility within a Complete Transactional Memory Stack. In: Proc. of the EuroSys2010 Conf., Paris, France (April 2010)Google Scholar
  3. 3.
    Dalessandro, L., Spear, M.F., Scott, M.L.: NOrec: Streamlining STM by Abolishing Ownership Records. In: Proc. of the 15th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, Bangalore, India (January 2010)Google Scholar
  4. 4.
    Dice, D., Shalev, O., Shavit, N.: Transactional Locking II. In: Proc. of the 20th Intl. Symp. on Distributed Computing, Stockholm, Sweden (September 2006)Google Scholar
  5. 5.
    Dice, D., Lev, Y., Moir, M., Nussbaum, D.: Early Experience with a Commercial Hardware Transactional Memory Implementation. In: Proc. of the 14th Intl. Conf. on Architectural Support for Programming Languages and Operating Systems, Washington, DC (March 2009)Google Scholar
  6. 6.
    Dice, D., Shavit, N.: TLRW: Return of the Read-Write Lock. In: Proc. of the 4th ACM SIGPLAN Workshop on Transactional Computing, Raleigh, NC (February 2009)Google Scholar
  7. 7.
    Diestelhorst, S., Hohmuth, M.: Hardware Acceleration for Lock-Free Data Structures and Software-Transactional Memory. In: Proc. of the Workshop on Exploiting Parallelism with Transactional Memory and other Hardware Assisted Methods, Boston, MA (April 2008)Google Scholar
  8. 8.
    Felber, P., Fetzer, C., Riegel, T.: Dynamic Performance Tuning of Word-Based Software Transactional Memory. In: Proc. of the 13th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, Salt Lake City, UT (February 2008)Google Scholar
  9. 9.
    Fernandes, S., Cachopo, J.: A Scalable and Efficient Commit Algorithm for the JVSTM. In: Proc. of the 5th ACM SIGPLAN Workshop on Transactional Computing, Paris, France (April 2010)Google Scholar
  10. 10.
    Fraser, K., Harris, T.: Concurrent Programming Without Locks. ACM Trans. on Computer Systems 25(2) (2007)Google Scholar
  11. 11.
    Herlihy, M.P., Luchangco, V., Moir, M., Scherer III, W.N.: Software Transactional Memory for Dynamic-sized Data Structures. In: Proc. of the 22nd ACM Symp. on Principles of Distributed Computing, Boston, MA (July 2003)Google Scholar
  12. 12.
    Herlihy, M.P., Moss, J.E.B.: Transactional Memory: Architectural Support for Lock-Free Data Structures. In: Proc. of the 20th Intl. Symp. on Computer Architecture, San Diego, CA (May 1993)Google Scholar
  13. 13.
    Herlihy, M.P., Wing, J.M.: Linearizability: a Correctness Condition for Concurrent Objects. ACM Trans. on Prog. Languages and Systems 12(3), 463–492 (1990)CrossRefGoogle Scholar
  14. 14.
    Hudson, R.L., Saha, B., Adl-Tabatabai, A.R., Hertzberg, B.: A Scalable Transactional Memory Allocator. In: Proc. of the 2006 Intl. Symp. on Memory Management, Ottawa, ON, Canada (June 2006)Google Scholar
  15. 15.
    Lev, Y., Luchangco, V., Marathe, V., Moir, M., Nussbaum, D., Olszewski, M.: Anatomy of a Scalable Software Transactional Memory. In: Proc. of the 4th ACM SIGPLAN Workshop on Transactional Computing, Raleigh, NC (February 2009)Google Scholar
  16. 16.
    Marathe, V., Moir, M.: Toward High Performance Nonblocking Software Transactional Memory. In: Proc. of the 13th ACM SIGPLAN Symp. on Principles and Practice of Parallel Programming, Salt Lake City, UT (February 2008)Google Scholar
  17. 17.
    Marathe, V.J., Spear, M.F., Scott, M.L.: Scalable Techniques for Transparent Privatization in Software Transactional Memory. In: Proc. of the 37th Intl. Conf. on Parallel Processing, Portland, OR (September 2008)Google Scholar
  18. 18.
    Menon, V., Balensiefer, S., Shpeisman, T., Adl-Tabatabai, A.R., Hudson, R., Saha, B., Welc, A.: Practical Weak-Atomicity Semantics for Java STM. In: Proc. of the 20th ACM Symp. on Parallelism in Algorithms and Architectures, Munich, Germany (June 2008)Google Scholar
  19. 19.
    Ni, Y., Welc, A., Adl-Tabatabai, A.R., Bach, M., Berkowits, S., Cownie, J., Geva, R., Kozhukow, S., Narayanaswamy, R., Olivier, J., Preis, S., Saha, B., Tal, A., Tian, X.: Design and Implementation of Transactional Constructs for C/C++. In: Proc. of the 23rd ACM SIGPLAN Conf. on Object Oriented Programming Systems Languages and Applications, Nashville, TN, USA (October 2008)Google Scholar
  20. 20.
    Olszewski, M., Cutler, J., Steffan, J.G.: JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory. In: Proc. of the 16th Intl. Conf. on Parallel Architecture and Compilation Techniques, Brasov, Romania (September 2007)Google Scholar
  21. 21.
    Shavit, N., Touitou, D.: Software Transactional Memory. In: Proc. of the 14th ACM Symp. on Principles of Distributed Computing, Ottawa, ON, Canada (August 1995)Google Scholar
  22. 22.
    Shpeisman, T., Menon, V., Adl-Tabatabai, A.R., Balensiefer, S., Grossman, D., Hudson, R.L., Moore, K., Saha, B.: Enforcing Isolation and Ordering in STM. In: Proc. of the 2007 ACM SIGPLAN Conf. on Programming Language Design and Implementation, San Diego, CA (June 2007)Google Scholar
  23. 23.
    Spear, M.: Lightweight, Robust Adaptivity for Software Transactional Memory. In: Proc. of the 22nd ACM Symp. on Parallelism in Algorithms and Architectures, Santorini, Greece (June 2010)Google Scholar
  24. 24.
    Spear, M.F., Dalessandro, L., Marathe, V.J., Scott, M.L.: Ordering-Based Semantics for Software Transactional Memory. In: Proc. of the 12th Intl. Conf. On Principles Of DIstributed Systems, Luxor, Egypt (December 2008)Google Scholar
  25. 25.
    Spear, M.F., Michael, M.M., von Praun, C.: RingSTM: Scalable Transactions with a Single Atomic Instruction. In: Proc. of the 20th ACM Symp. on Parallelism in Algorithms and Architectures, Munich, Germany (June 2008)Google Scholar
  26. 26.
    Spear, M.F., Shriraman, A., Dalessandro, L., Dwarkadas, S., Scott, M.L.: Nonblocking Transactions Without Indirection Using Alert-on-Update. In: Proc. of the 19th ACM Symp. on Parallelism in Algorithms and Architectures, San Diego, CA (June 2007)Google Scholar
  27. 27.
    Tabba, F., Wang, C., Goodman, J.R., Moir, M.: NZTM: Nonblocking Zero-Indirection Transactional Memory. In: Proc. of the 2nd ACM SIGPLAN Workshop on Transactional Computing, Portland, OR (August 2007)Google Scholar
  28. 28.
    Wang, C., Chen, W.Y., Wu, Y., Saha, B., Adl-Tabatabai, A.R.: Code Generation and Optimization for Transactional Memory Constructs in an Unmanaged Language. In: Proc. of the 2007 Intl. Symp. on Code Generation and Optimization, San Jose, CA (March 2007)Google Scholar
  29. 29.
    Yourst, M.: PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator. In: Proc. of the 2007 IEEE Intl. Symp. on Performance Analysis of Systems and Software, San Jose, CA (April 2007)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Francois Carouge
    • 1
  • Michael Spear
    • 1
  1. 1.Lehigh University 

Personalised recommendations