Scalable Object-Aware Hardware Transactional Memory

  • Behram Khan
  • Matthew Horsnell
  • Mikel Lujan
  • Ian Watson
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6271)

Abstract

A Hardware Transactional Memory (HTM) aids the construction of lock-free regions within applications with fewer concerns about correctness and potentially greater performance through optimistic concurrency. Object-aware hardware adds a level of indirection to memory accesses, memory addresses become a combination of the object being accessed and the offset within it. The hardware maintains a mapping from objects to memory locations just as a mapping from virtual to real memory is handled through page tables. In a scalable object-aware system the directories are addressed by objects identifiers.

In this paper we extend a scalable object-aware memory system to implement a HTM. Our object-aware protocol permits locks on directories to be avoided for objects only read during a transaction. Working at the granularity of an object allows entries within the directories to be associated with multiple cache lines, as opposed to one, and reduce the amount of network traffic. Finally, our commit protocol dispenses with the need for a centrally controlled transaction ID order.

Keywords

Scalable Hardware transactional memory Object-oriented Multi-core architecture Concurrency Atomicity 

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Ansari, M., Kotselidis, C., Watson, I., Kirkham, C., Luján, M., Jarvis, K.: Lee-TM: A non-trivial benchmark suite for transactional memory. In: Bourgeois, A.G., Zheng, S.Q. (eds.) ICA3PP 2008. LNCS, vol. 5022, pp. 196–207. Springer, Heidelberg (2008)CrossRefGoogle Scholar
  2. 2.
    Scherer III, W.N., Scott, M.L.: Advanced Contention Management for Dynamic Software Transactional Memory. In: 24th ACM Symp. on Principles of Distributed Computing (2005)Google Scholar
  3. 3.
    Khan, B., Horsnell, M., Rogers, I., Luján, M., Dinn, A., Watson, I.: A First Insight into Object-Aware Hardware Transactional Memory. In: Proc. SPAA (2008)Google Scholar
  4. 4.
    Khan, B., Horsnell, M., Rogers, I., Luján, M., Dinn, A., Watson, I.: An Object-Aware Hardware Transactional Memory System. In: Proc. HPCC (2008)Google Scholar
  5. 5.
    Minh, C., Trautmann, M., Chung, J., McDonald, A., Bronson, N., Casper, J., Kozyrakis, C., Olukotun, K.: An effective hybrid transactional memory system with strong isolation guarantees. In: Proc. ISCA, pp. 69–80 (2007)Google Scholar
  6. 6.
    Moore, K., Bobba, J., Moravan, M., Hill, M., Wood, D.: LogTM: Log-based transactional memory. In: Proc. HPCA, pp. 258–269 (2006)Google Scholar
  7. 7.
    Rajwar, R., Goodman, J.R.: Transactional Lock-Free Execution of Lock-Based Programs. In: Proc. of the Tenth Intl. Conference on Architectural Support for Programming Languages and Operating Systems (2002)Google Scholar
  8. 8.
    Watson, I., Kirkham, C., Luján, M.: A study of a transactional parallel routing algorithm. In: Proceedings of the 16th International Conference on Parallel Architecture and Compilation Techniques, pp. 388–398 (2007)Google Scholar
  9. 9.
    Williams, I.: Object-Based Memory Architecture. PhD thesis, Department of Computer Science, University of Manchester (1989)Google Scholar
  10. 10.
    Wright, G., Seidl, M., Wolczko, M.: An Object-aware Memory Architecture. Science of Computer Programming 62(2), 145–163 (2006)MathSciNetCrossRefMATHGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Behram Khan
    • 1
  • Matthew Horsnell
    • 1
  • Mikel Lujan
    • 1
  • Ian Watson
    • 1
  1. 1.School of Computer ScienceThe University of ManchesterUK

Personalised recommendations