The Glitch PUF: A New Delay-PUF Architecture Exploiting Glitch Shapes

  • Daisuke Suzuki
  • Koichi Shimizu
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6225)

Abstract

In this paper we propose a new Delay-PUF architecture that is expected to solve the current problem of Delay-PUF that it is easy to predict the relation between delay information and generated information. Our architecture exploits glitches that behave non-linearly from delay variation between gates and the characteristic of pulse propagation of each gate. We call this architecture Glitch PUF. In this paper, we present a concrete structure of Glitch PUF. We then show the evaluation results on the randomness and statistical properties of Glitch PUF. In addition, we present a simple scheme to evaluate Delay-PUFs by simulation at the design stage. We show the consistency of the evaluation results for real chips and those by simulation for Glitch PUF.

References

  1. 1.
    Pappu, R.S.: Physical One-way Functions. Ph.D. Thesis, M.I.T. (2001), http://pubs.media.mit.edu/pubs/papers/01.03.pappuphd.powf.pdf
  2. 2.
    Dodis, Y., Reyzin, M., Smith, A.: Fuzzy Extractors: How to Generate Strong Keys from Biometrics and Other Noisy Data. In: Cachin, C., Camenisch, J.L. (eds.) EUROCRYPT 2004. LNCS, vol. 3027, pp. 523–540. Springer, Heidelberg (2004)CrossRefGoogle Scholar
  3. 3.
    Tuyls, P., Batina, L.: RFID-Tags for Anti-Counterfeiting. In: Pointcheval, D. (ed.) CT-RSA 2006. LNCS, vol. 3860, pp. 115–131. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  4. 4.
    Gassend, B., Clarke, D., van Dijk, M., Devadas, S.: Silicon Physical Random Functions. In: Proc., of the 9th ACM Conference on Computer and Communications Security (CCS 2002), pp. 148–160 (2002)Google Scholar
  5. 5.
    Guajardo, J., Kumar, S.S., S̃chrijen, G.J., Tuyls, P.: FPGA Intrinsic PUFs and Their Use for IP Protection. In: Paillier, P., Verbauwhede, I. (eds.) CHES 2007. LNCS, vol. 4727, pp. 63–80. Springer, Heidelberg (2007)CrossRefGoogle Scholar
  6. 6.
    Lee, J.W., Lim, D., Gassend, B., Suh, G.E., van Dijk, M., Devadas, S.: A Technique to Build a Secret Key in Integrated Circuits for Identification and Authentication Applications. In: Proc. of the IEEE VLSI Circuits Symposium, pp. 176–179 (2004)Google Scholar
  7. 7.
    Suh, G.E., Devadas, S.: Physical Unclonable Functions for Device Authentication and Secret Key Generation. In: Proc. of the 44th annual Design Automation Conference (DAC 2007), pp. 9–14 (2007)Google Scholar
  8. 8.
    Kumar, S.S., Guajardo, J., Maes, R., S̃chrijen, G.J., Tuyls, P.: Extended Abstract: The Butterfly PUF: Protecting IP on every FPGA. In: Proc. of the IEEE International Workshop on Hardware-Oriented Security and Trust 2008 (HOST 2008), pp. 67–70 (2008)Google Scholar
  9. 9.
    Majzoobi, M., Koushanfar, F., Potkonjak, M.: Lightweight secure PUFs. In: Proc. of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD 2008), pp. 670–673 (2008)Google Scholar
  10. 10.
    B̈osch, C., Guajardo, J., Sadeghi, A.R., Shokrollahi, J., Tuyls, P.: Efficient Helper Data Key Extractor on FPGAs. In: Oswald, E., Rohatgi, P. (eds.) CHES 2008. LNCS, vol. 5154, pp. 181–197. Springer, Heidelberg (2008)CrossRefGoogle Scholar
  11. 11.
    Maes, R., Tuyls, P., Verbauwhede, I.: Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs. In: Proc. of the 2009 IEEE International Symposium on Information Theory (ISIT 2009), pp. 2101–2105 (2009)Google Scholar
  12. 12.
    Maes, R., Tuyls, P., Verbauwhede, I.: A Soft Decision Helper Data Algorithm for SRAM PUFs. In: Clavier, C., Gaj, K. (eds.) CHES 2009. LNCS, vol. 5747, pp. 332–347. Springer, Heidelberg (2009)CrossRefGoogle Scholar
  13. 13.
    Chopra, J., Colopy, R.L.: SRAM Characteristics as Physical Unclonable Functions. Worcester Polytechnic Institute Electric Project Collection (2009), http://www.wpi.edu/Pubs/E-project/Available/E-project-031709-141338/
  14. 14.
    Rührmair, U., Sölter, J., Sehnke, F.: On the Foundations of Physical Unclonable Functions. Cryptology ePrint Archive, 2009/277 (2009)Google Scholar
  15. 15.
    Najm, F.N., Menezes, N.: Statistical Timing Analysis Based on a Timing Yield Model. In: Proc. of the 41st annual Design Automation Conference (DAC 2004), pp. 460–465 (2004)Google Scholar
  16. 16.
    Standard Delay Format Specification version 3.0 (1995), http://www.eda.org/sdf/sdf_3.0.pdf
  17. 17.
    Hiramoto, T., Takeuchi, K., Nisida, A.: Variability of Characterisics in Scaled MOSFETs. J. IEICE 92(6), 416–426 (2009)Google Scholar
  18. 18.
    Berkelaar, M.: Statistical Delay Calculation, a Linear Time Method. In: Proc. of the International Workshop on Timing Analysis (TAU’97), pp. 15–24 (1997)Google Scholar
  19. 19.
    Ignatenko, T., Schrijen, G.J., Skoric, B., Tuyls, P., Willems, F.: Estimating the Secrecy-Rate of Physical Unclonable Functions with the Context-Tree Weighting Method. In: Proc. of the 2006 IEEE International Symposium on Information Theory (ISIT 2006), pp. 499–503 (2006)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Daisuke Suzuki
    • 1
    • 2
  • Koichi Shimizu
    • 1
  1. 1.Information Technology R&D CenterMitsubishi Electric Corporation 
  2. 2.Graduate School of Environmental and Information SciencesYokohama National University 

Personalised recommendations