Fair and Comprehensive Methodology for Comparing Hardware Performance of Fourteen Round Two SHA-3 Candidates Using FPGAs

  • Kris Gaj
  • Ekawat Homsirikamol
  • Marcin Rogawski
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6225)

Abstract

Performance in hardware has been demonstrated to be an important factor in the evaluation of candidates for cryptographic standards. Up to now, no consensus exists on how such an evaluation should be performed in order to make it fair, transparent, practical, and acceptable for the majority of the cryptographic community. In this paper, we formulate a proposal for a fair and comprehensive evaluation methodology, and apply it to the comparison of hardware performance of 14 Round 2 SHA-3 candidates. The most important aspects of our methodology include the definition of clear performance metrics, the development of a uniform and practical interface, generation of multiple sets of results for several representative FPGA families from two major vendors, and the application of a simple procedure to convert multiple sets of results into a single ranking.

Keywords

benchmarking hash functions SHA-3 FPGA 

References

  1. 1.
    Nechvatal, J., et al.: Report on the Development of the Advanced Encryption Standard (AES), http://csrc.nist.gov/archive/aes/round2/r2report.pdf
  2. 2.
  3. 3.
  4. 4.
    Gaj, K., Chodowiec, P.: Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays. In: Naccache, D. (ed.) CT-RSA 2001. LNCS, vol. 2020, pp. 84–99. Springer, Heidelberg (2001)CrossRefGoogle Scholar
  5. 5.
    Hwang, D., Chaney, M., Karanam, S., Ton, N., Gaj, K.: Comparison of FPGA-targeted Hardware Implementations of eSTREAM Stream Cipher Candidates. In: State of the Art of Stream Ciphers Workshop, SASC 2008, February, pp. 151–162 (2008)Google Scholar
  6. 6.
    Good, T., Benaissa, M.: Hardware Performance of eStream Phase-III Stream Cipher Candidates. In: State of the Art of Stream Ciphers Workshop, SASC 2008, February 2008, pp. 163–173 (2008)Google Scholar
  7. 7.
  8. 8.
  9. 9.
    Drimer, S.: Security for Volatile FPGAs. ch. 5: The Meaning and Reproducibility of FPGA Results. Ph.D. Dissertation, University of Cambridge, Computer Laboratory, uCAM-CL-TR-763 (Nov 2009)Google Scholar
  10. 10.
  11. 11.
    Tilich, S., et al.: High-speed Hardware Implementations of Blake, Blue Midnight Wish, Cubehash, ECHO, Fugue, Groestl, Hamsi, JH, Keccak, Luffa, Shabal, Shavite-3, SIMD, and Skein. Cryptology, ePrint Archive, Report 2009/510 (2009)Google Scholar
  12. 12.
    Kobayashi, K., et al.: Evaluation of Hardware Performance for the SHA-3 Candidates Using SASEBO-GII. Cryptology, ePrint Archive, Report 2010/010 (2010)Google Scholar
  13. 13.
    ECRYPT Benchmarking of Cryptographic Systems, http://bench.cr.yp.to
  14. 14.
    CERG GMU Group: Hardware Interface of a Secure Hash Algorithm (SHA), http://cryptography.gmu.edu/athena/index.php?id=interfaces
  15. 15.
    Meyer-Baese, U.: Digital Signal Processing with Field Programmable Gate Arrays, ch. 6, 7, 3rd edn., pp. 343–475. Springer, Heidelberg (2007)Google Scholar
  16. 16.
    van Lint, J.H.: Introduction to Coding Theory, 2nd edn. Springer, Heidelberg (1992)MATHGoogle Scholar
  17. 17.
    Gaj, K., Chodowiec, P.: FPGA and ASIC Implementations of AES. In: Cryptographic Engineering, ch. 10, pp. 235–294. Springer, Heidelberg (2009)CrossRefGoogle Scholar
  18. 18.
    ATHENa Project Website, http://cryptography.gmu.edu/athena
  19. 19.
    Chaves, R., Kuzmanov, G., Sousa, L., Vassiliadis, S.: Improving SHA-2 Hardware Implementations. In: Goubin, L., Matsui, M. (eds.) CHES 2006. LNCS, vol. 4249, pp. 298–310. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  20. 20.
    Chaves, R., Kuzmanov, G., Sousa, L., Vassiliadis, S.: Cost Efficient SHA Hardware Accelerators. IEEE Trans. Very Large Scale Integration Systems 16, 999–1008 (2008)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Kris Gaj
    • 1
  • Ekawat Homsirikamol
    • 1
  • Marcin Rogawski
    • 1
  1. 1.ECE DepartmentGeorge Mason UniversityFairfaxU.S.A.

Personalised recommendations