Developing a Hardware Evaluation Method for SHA-3 Candidates

  • Luca Henzen
  • Pietro Gendotti
  • Patrice Guillet
  • Enrico Pargaetzi
  • Martin Zoller
  • Frank K. Gürkaynak
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6225)

Abstract

The U.S. National Institute of Standards and Technology encouraged the publication of works that investigate and evaluate the performances of the second round SHA-3 candidates. Besides the hardware characterization of the 14 candidate algorithms, the main goal of this paper is the description of a reliable methodology to efficiently characterize and compare VLSI circuits of cryptographic primitives. We took the opportunity to apply it on the ongoing SHA-3 competition. To this end, we implemented several architectures in a 90 nm CMOS technology, targeting high- and moderate-speed constraints separately. Thanks to this analysis, we were able to present a complete benchmark of the achieved post-layout results of the circuits.

References

  1. 1.
    De Cannière, C., Rechberger, C.: Finding SHA-1 characteristics: General results and applications. In: Lai, X., Chen, K. (eds.) ASIACRYPT 2006. LNCS, vol. 4284, pp. 1–20. Springer, Heidelberg (2006)CrossRefGoogle Scholar
  2. 2.
    De Cannière, C., Rechberger, C.: Preimages for reduced SHA-0 and SHA-1. In: Wagner, D. (ed.) CRYPTO 2008. LNCS, vol. 5157, pp. 179–202. Springer, Heidelberg (2008)Google Scholar
  3. 3.
    El-Hadedy, M., Gligoroski, D., Knapskog, S.J., Aas, E.J.: Low area FPGA and ASIC implementations of the hash function “Blue Midnight Wish-256”. In: International Conference on Computer Engineering & Systems, ICCES 2009, Cairo, pp. 10–14 (2009)Google Scholar
  4. 4.
    Gürkaynak, F.K., Henzen, L., Gendotti, P., Guillet, P., Pargaetzi, E., Zoller, M.: Hardware evaluation of the second-round SHA-3 candidate algorithms (2010), http://www.iis.ee.ethz.ch/~sha3/
  5. 5.
    Gürkaynak, F.K., Luethi, P., Bernold, N., Blattmann, R., Goode, V., Marghitola, M., Kaeslin, H., Felber, N., Fichtner, W.: Hardware evaluation of eSTREAM candidates: Achterbahn, grain, mickey, mosquito, sfinks, trivium, vest, zk-crypt. eSTREAM, ECRYPT Stream Cipher Project, Report 2006/015 (2006), http://www.ecrypt.eu.org/stream
  6. 6.
    Kaeslin, H.: Digital Integrated Circuit Design, from VLSI Architectures to CMOS Fabrication. Cambridge University Press, Cambridge (2008)MATHGoogle Scholar
  7. 7.
    Kobayashi, K., Ikegami, J., Matsuo, S., Sakiyama, K., Ohta, K.: Evaluation of hardware performance for the SHA-3 candidates using SASEBO-GII. Cryptology ePrint Archive, Report 2010/010 (2010), http://eprint.iacr.org/
  8. 8.
    Namin, A.H., Hasan, M.A.: Hardware implementation of the compression function for selected SHA-3 candidates. CACR 2009-28 (2009), http://www.vlsi.uwaterloo.ca/~ahasan/hasan_report.html
  9. 9.
    NIST. Announcing request for candidate algorithm nominations for a new cryptographic hash algorithm (SHA-3) family. Federal Register 72(212) (2007), http://www.nist.gov/hash-competition
  10. 10.
    Tillich, S., Feldhofer, M., Issovits, W., Kern, T., Kureck, H., Mühlberghuber, M., Neubauer, G., Reiter, A., Köfler, A., Mayrhofer, M.: Compact hardware implementations of the SHA-3 candidates ARIRANG, BLAKE, Grøstl, and Skein. Cryptology ePrint Archive: Report 2009/349 (2009)Google Scholar
  11. 11.
    Tillich, S., Feldhofer, M., Kirschbaum, M., Plos, T., Schmidt, J.-M., Szekely, A.: High-speed hardware implementations of BLAKE, Blue Midnight Wish, CubeHash, ECHO, Fugue, Grøstl, Hamsi, JH, Keccak, Luffa, Shabal, SHAvite-3, SIMD, and Skein. Cryptology ePrint Archive, Report 2009/510 (2009)Google Scholar
  12. 12.
    Wang, X., Yu, H.: How to break MD5 and other hash functions. In: Cramer, R. (ed.) EUROCRYPT 2005. LNCS, vol. 3494, pp. 19–35. Springer, Heidelberg (2005)CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Luca Henzen
    • 1
  • Pietro Gendotti
    • 2
  • Patrice Guillet
    • 2
  • Enrico Pargaetzi
    • 2
  • Martin Zoller
    • 2
  • Frank K. Gürkaynak
    • 3
  1. 1.Integrated Systems LaboratoryETH Zurich 
  2. 2.Department of Information Technology and Electrical EnginneringETH Zurich 
  3. 3.Microelectronics Designs CenterETH Zurich 

Personalised recommendations