Design of a CABAC Encoder

Chapter
First Online:
Part of the Signals and Communication Technology book series (SCT)

Abstract

In this chapter, architecture of a typical hardware (HW) CABAC encoder is illustrated. The design methodology of a SoC (System-on-Chip) based entropy coder is first presented. Based on the design methodology, hardware/software (HW/SW) functional partitioning of CABAC encoder function is carried out to decide which functions are to be designed in HW and which functions are to be processed on host processor. Furthermore, the strategy of functional partitioning of HW encoder is applied, and the top-level function blocks and encoding flow of the encoder are introduced. In the subsequent sections, design details of major functional blocks are presented including binarization and bin packet generation and binary arithmetic coding (BAC). Finally, additional functions supported by the encoder including context model initialization, RDO function support in BAC are discussed.

Keywords

Context Model Residual Block Host Processor Context Line FIFO Buffer 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
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Copyright information

© Springer-Verlag Berlin Heidelberg 2011

Authors and Affiliations

  1. 1.Dept. Electrical & Computer EngineeringNational University of SingaporeSingaporeSingapore
  2. 2.St-LaurentCanada

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