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Power Analysis of Single-Rail Storage Elements as Used in MDPL

  • Amir Moradi
  • Thomas Eisenbarth
  • Axel Poschmann
  • Christof Paar
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 5984)

Abstract

Several dual-rail logic styles make use of single-rail flip-flops for storing intermediate states. We show that single mask bits, as applied by various side-channel resistant logic styles such as MDPL and iMDPL, are not sufficient to obfuscate the remaining leakage of single-rail flip-flops.

By applying simple models for the leakage of masked flip-flops, we design a new attack on circuits implemented using masked single-rail flip-flops. Contrary to previous attacks on masked logic styles, our attack does not predict the mask bit and does not need detailed knowledge about the attacked device, e.g., the circuit layout. Moreover, our attack works even if all the load capacitances of the complementary signals are perfectly balanced and even if the PRNG is ideally unbiased. Finally, after performing the attack on DRSL, MDPL, and iMDPL circuits we show that single-bit masks do not influence the exploitability of the revealed leakage of the masked flip-flops.

Keywords

Information Leakage Combinational Circuit Hold Phase Power Trace Leakage Model 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Amir Moradi
    • 1
  • Thomas Eisenbarth
    • 1
  • Axel Poschmann
    • 2
  • Christof Paar
    • 1
  1. 1.Horst Görtz Institute for IT SecurityRuhr University BochumGermany
  2. 2.Division of Mathematical SciencesNanyang Technological UniversitySingapore

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