Application Specific Processors for the Autoregressive Signal Analysis

  • Anatolij Sergiyenko
  • Oleg Maslennikow
  • Piotr Ratuszniak
  • Natalia Maslennikowa
  • Adam Tomas
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6067)

Abstract

Two structures of the processors for the autoregressive analysis are considered. The first of them implements the Durbin algorithm using the rational fraction calculations. Such calculations provide higher precision than integer calculations do, and are simpler than the floating point calculations. The second of them implements the adaptive lattice filter. These processors are configured in FPGA, and give the possibility of the signal analysis with the sampling frequency up to 300 MHz.

They provide new opportunities for the real time signal analysis and adaptive filtering in radio receivers, ultrasonic devices, wireless communications, etc.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. 1.
    Candy, F.V.: Model-Based Signal Processing, p. 677. Wiley, Hoboken (2006)Google Scholar
  2. 2.
    Brent, R.P.: Old and new algorithms for Toeplitz systems. In: Proc. SPIE. Advanced Algorithms and Architectures for Signal Processing III, vol. 975. SPIE, Bellingham (1989)Google Scholar
  3. 3.
    Bojanchuk, A.W., Brent, R.P., de Hoog, F.R.: Linearly Connected Arrays for Toeplitz Least-Squares Problems. J. of Parallel and Distributed Computing 9, 261–270 (1990)CrossRefGoogle Scholar
  4. 4.
    Sergyienko, A., Maslennikow, O.: Implementation of Givens QR Decomposition inFPGA. In: Wyrzykowski, R., Dongarra, J., Paprzycki, M., Waśniewski, J. (eds.) PPAM 2001. LNCS, vol. 2328, pp. 453–459. Springer, Heidelberg (2002)Google Scholar
  5. 5.
    Sergyienko, A., Maslennikow, O., Lepekha, V.: FPGA Implementation of the Conjugate Gradient Method. In: Wyrzykowski, R., Dongarra, J., Meyer, N., Waśniewski, J. (eds.) PPAM 2005. LNCS, vol. 3911, pp. 526–533. Springer, Heidelberg (2006)Google Scholar
  6. 6.
    Karlström, P., Ehliar, A., Liu, D.: High performance, low latency FPGA based floating point adder and multiplier units in a Virtex4. In: 24th IEEE Norchip Conf., Linköping, Sweden, November 20-21, pp. 31–34 (2006)Google Scholar
  7. 7.
    Widrow, B., Stearns, S.D.: Adaptive Signal Processing. Prentice-Hall, Englewod Clifs (1985)MATHGoogle Scholar
  8. 8.
    Pohl, Z., Matouek, R., Kadlec, J., Tichý, M., Lícko, M.: Lattice adaptive filter implementation for FPGA. In: Proc. 2003 ACM/SIGDA 11th Int. Symp., Monterey, California, USA, pp. 246–250 (2003)Google Scholar
  9. 9.
    Hwang, Y.T., Han, J.C.: A novel FPGA design of a high throughput rate adaptive prediction error filter. In: 1st IEEE Asia Pacific Conf. on ASICs, AP-ASIC 1999, pp. 202–205 (1999)Google Scholar
  10. 10.
    Lin, A.Y., Gugel, K.S.: Feasibility of fixed-point transversal adaptive filters in FPGA devices with embedded DSP blocks. In: 3rd IEEE IWSOC 2003, pp. 157–160 (2003)Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Anatolij Sergiyenko
    • 1
  • Oleg Maslennikow
    • 2
  • Piotr Ratuszniak
    • 2
  • Natalia Maslennikowa
    • 2
  • Adam Tomas
    • 3
  1. 1.National Technical University of UkraineKievUkraine
  2. 2.Koszalin University of TechnologyKoszalinPoland
  3. 3.Czȩstochowa University of TechnologyCzȩstochowaPoland

Personalised recommendations