Introducing a Performance Model for Bandwidth-Limited Loop Kernels

  • Jan Treibig
  • Georg Hager
Part of the Lecture Notes in Computer Science book series (LNCS, volume 6067)


We present a diagnostic performance model for bandwidth-limited loop kernels which is founded on the analysis of modern cache based microarchitectures. This model allows an accurate performance prediction and evaluation for existing instruction codes. It provides an in-depth understanding of how performance for different memory hierarchy levels is made up. The performance of raw memory load, store and copy operations and a stream vector triad are analyzed and benchmarked on three modern x86-type quad-core architectures in order to demonstrate the capabilities of the model.


Main Memory Cache Line Instruction Code Cache Level Memory Level 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2010

Authors and Affiliations

  • Jan Treibig
    • 1
  • Georg Hager
    • 1
  1. 1.Regionales Rechenzentrum ErlangenUniversity Erlangen-Nuernberg 

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